Open-Silicon .:. Virtual Prototyping
Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

The world of Virtual Prototyping

A virtual prototype is a software executable version of a hardware system that is created from functional models developed using high level languages like C/C++ or SystemC or generated from RTL. The models can either be cycle accurate which is required for performance analysis or fast functional accurate which enables early software development.

Below video provides an overview of virtual prototype:

Virtual prototyping in a SoC design flow brings in two key benefits:

1. Dynamic performance analysis in architecture phase, ensuring correct-by-design approach. The virtual prototyping solution enables designers to quickly develop a fully functional and cycle accurate system with moderate to minimal efforts. It is possible to run different use cases with different traffic requirements and measure the load, threshold, and resource utilization. This gives an early indication of changes required at the design phase rather than finding issues at a later stage in implementation and verification phase. Below video illustrates how Open-Silicon does performance analysis using virtual prototypes:

2. Early software development in pre-silicon phase, enabling faster time to market.  The virtual prototyping solution enables software developers to quickly jump start software development and testing. The software quality can be improved because virtual prototyping systems can allow lengthier, automated testing of software. Moreover, the platform gives a whole set of debug features like debugging signals, viewing/editing registers, viewing/editing memories, source code level debug etc.  Software Design Moves Virtual Prototyping Into The Mainstream

Open-Silicon Memory Model IPs

To enable firmware and software developers to boot SoCs from flash memories (NOR, SD and eMMC) in a virtual environment, Open-Silicon has implemented models from memory specifications. These models can be integrated into a virtual prototype and allows firmware developers to write and validate boot-ROM and boot loaders. Also device drivers for these memories can be validated.

The original version of the models are implemented in Verilog HDL and so these can be used in RTL simulator as well. The main features of the memory models are:

SD Memory:

  • Standard SD 3.0 interface.
  • 4-bit bus width.
  • Single and multi-block memory read write.
  • Supports DDR transfer
  • Storage up to 2MB.( This is limited for demo)
  • Supports most of the SD standard commands

SNOR memory:

  • Supports SPI/Dual/Quad bus modes
  • Supports Simple mode read/write access to memory
  • Supports DDR transfer
  • Standard memory registers

eMMC memory:

  • Supports JESD84-B451 standard.
  • Supports 8-bit data mode, storage size up to 1MB.
  • Supports Class 0, 2, 4 command sets.
  • Set of registers for operation control and status.
  • Supports DDR transfer

NAND memory:

  • Supports ONFI 1.0 standard interface and command set
  • Supports
    • Data width x8
    • Page size 2K + 64 bytes spare area
    • Block size 64 pages
  • Supports page program/erase
  • Supports random data output
  • Supports register and ID read commands

Open-Silicon Virtual Prototyping Flow

Open-Silicon has been using virtual prototyping in SoC designs since 2012 and has successfully deployed it for complex SoC designs. It has helped mitigate design risks and also allowed early firmware & software development, thereby reducing overall schedule.

The following figure depicts the virtual prototyping methodology in place at Open-Silicon:


Virtual Prototyping Ecosystem:


Contact Sales:

For more information, please contact