Our conversation addresses high-performance computing/networking SoC design challenges and how specialized IP subsystems are keeping designers ahead of the curve.
Editor’s Note: High-performance networking applications are what Open-Silicon is addressing with its end-to-end ASIC offering, as the company’s president and CEO, Taher Madraswala, noted recently. To learn more, EECatalog spoke recently with Swamy Irrinki, Open-Silicon’s Senior Director of Marketing, and Kalpesh Sanghvi, the company’s Technical Manager for IP and Platforms. Edited excerpts of our Q&A follow.
Embedded Systems Engineering (ESE): Could we begin by introducing our readers to Open-Silicon?
Swamy Irrinki, Open-Silicon’s Senior Director of Marketing (SI): Open-Silicon is a turnkey ASIC solution company that develops complete custom SoC solutions for its customers. We design, manufacture and deliver the fully tested silicon parts. We can complete the entire project, from spec to chip, or we can step in and engage at any stage within the process; whether it’s simply a conceptual design idea that a customer is envisioning, a full spec design, or something further down the line; perhaps at the RTL, netlist or GDS stage.
We’ve completed more than 300 designs and shipped more than 135 million ASIC units at a quality level of 30 DPPM on average. We take pride in our track record of shipping high quality custom silicon on time and on budget. Unlike companies that focus only on design or only on manufacturing, we remain fully engaged at every step. Therefore, it behooves us to employ a very robust design methodology that utilizes thorough checklists, and rigorous verification and test throughout the process. This methodology is based on the knowledge and experience of our design and manufacturing teams, all of whom are dedicated to seeing the design through to high volume silicon production.
ESE: What is the biggest challenge facing the ASIC market and how is Open-Silicon addressing it?
SI: Market applications, like high performance computing (HPC), are putting a great deal of performance demands on ASIC designs. The result is highly complex ASIC designs that require multiple IPs capable of satisfying the design and performance requirements associated with these applications. We’ve been able to stay well ahead of the market by relying on the 3rd party IP ecosystem for most of the standard IPs, which enables us to find the best IP solution in the market and deliver optimized custom SoCs to our customers. We’ve also developed our own niche IPs that are strategic to our focus on high performance, high speed and high bandwidth computing applications. Our solutions include the Interlaken IP subsystem [Interlaken IP + Forward Error Correction (FEC) IP], Ethernet IP subsystem [Flexible Ethernet (FlexE) IP + Ethernet PCS IP + Forward Error Correction (FEC) IP + Packet Interface IP + ODU Interface IP] for high end networking applications. We also have a high performance memory subsystem for HMC and HBM. The high bandwidth memory subsystem [HBM2 Controller + HBM2 PHY + 2.5D I/O] is very much tied to ASIC technology for HPC applications like AI, deep learning, machine learning, as well as networking and cloud computing (Figure 1).
ESE: Please discuss for our readers how the Interlaken IP subsystem can be capitalized upon as a differentiator when developing networking solutions.
Kalpesh Sanghvi, Technical Manager for IP and Platforms at Open-Silicon (KS): Interlaken IP was introduced about twelve years ago by tier-one OEM Cisco, and later adopted by Xilinx, Broadcom and others. Today, these companies along with Open-Silicon, are part of the Interlaken Alliance consortium, and this particular IP was really targeted for chip-to-chip communication for very high bandwidth applications. Most chips with Interlaken IP are found in networking applications. You can imagine all the different chips that go in a line card or switch fabric, or the chips for the framer/mapper or NPU or TCAM or quality management ASIC for the switch fabric—all of them are running at a very high speed, and the demand for very low latency drove the need for Interlaken, which has since been adopted by all the major networking companies.
Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The updated Interlaken specification is capable of supporting SerDes beyond 30Gbps and up to 58Gbps—this was mainly because of the introduction of the peer-to-peer service, which allows sending more data on fewer lines. This led to development of Open-Silicon’s eighth generation Interlaken IP core, supporting up to 1.2 Tbps high performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). https://www.open-silicon.com/open-silicon-ips/interlaken-controller-ip/
Forward Error Correction for the Interlaken protocol came into the picture last year. It was mainly borrowed from the IEEE 802.3 Ethernet spec, with some minor tweaks. Since Open-Silicon supports both Interlaken IP and Ethernet IP, we developed the FEC IP that supports both the Interlaken protocol and Ethernet protocol for high performance computing and networking applications.
ESE: What makes Open-Silicon’s Ethernet IP Subsystem Solution “comprehensive” and why is comprehensiveness important?
KS: With Interlaken and FEC IP in our portfolio (Figure 2), we looked at what other IPs we could develop for networking by leveraging our expertise in high speed interface IPs. This led to development of our Ethernet IP Subsystem (Figure 3). It includes PCS, FlexE, FEC, Packet I/F and ODU I/F, and is optimized for gate count, performance and configurability.
Because there is a lot of tight coupling between these IP blocks, it makes sense, and mitigates common integration issues, to have all of them supplied by a single vendor, rather than having to deal with different IP blocks from different vendors that may or may not be optimized for compatibility within the same design. By developing all these IPs together, we were able to see which components could be fused, and what configuration options we could provide for our customers to make it easy for them to use for their applications.
These are the reasons why a comprehensive networking IP subsystem, including both an Interlaken IP subsystem and Ethernet IP subsystem, is important. 
ESE: That would save customers time.
KS: The time pressure is real. Customers are challenged to integrate and interface with other vendors’ IP, and it becomes difficult because they must meet the performance, and they have to meet the required application use cases for a variety of scenarios. It becomes highly difficult for the customer to integrate these pieces from different vendors.
ESE: What networking challenges are we going to see grow over the next five years and why?
KS: Because the demand for data is growing exponentially, you’ll see the technology that is in place today aging much more quickly. To address this issue, we have developed a proven IP solution that is scalable, and therefore capable of supporting the next generation of high performance systems.
Looking back (Figure 4), we see that 10GbE was the standard for a relatively long period, followed by 40GbE. In more recent years, however, the rate at which the different speeds and different standards have been introduced is growing at a very fast pace, moving to 50GbE, 100GbE and beyond.
So, there are definitely going to be challenges to meet the data requirements on the networking side. Performance is one of these. The standards are evolving, and you need support for all the different standards, as well as compatibility to old standards for legacy installations.
The best way to understand what has been driven by all the major networking companies and what they plan to pursue beyond them, is keeping up to date on what’s happening in standards forums. So, we are keeping a very close watch on all the different standards on the networking side to make sure our IP is very much in line with those standards and meets all the requirements.
ESE: Could you speak a bit more about the standards?
KS: The standards are complex and come in so many different flavors. It’s critical that we keep our finger on the pulse of all of them. We are constantly talking to customers to learn about their next gen requirements. For example, some customers are talking about FlexE 2.0, but that standard is not yet ratified. It will be ratified sometime in Q3 or Q4 of this year. However, we’re making sure that our FlexE IP will be capable of accommodating the standard well before it goes into a customer’s FlexE 2.0 spec design.
ESE: What insights did you gain at OFC 2018?
KS: We believe the OFC is a forum that we should participate in more and more because it enables us to see what standards are evolving, and what solutions are being demonstrated, like FlexE. So, we get to learn all the different things that the standards communities, customers and eco-system partners are doing. It’s a perfect place to get feedback, hear about changes to the spec, and get some insight about where the market is heading.
OFC also gives us the opportunity to meet customers and learn about their latest products, as well as those that will be deployed a year or two down the line.
We get to see customers who develop the test equipment for the new standards and the new protocols. That allows us to understand where the market is heading and what options are available to test our IP as well.
Overall, we get inputs from all the angles: from the customer viewpoint, from the standards communities, and from other vendors with support tools for the IP ecosystem.
SI: At OFC we saw 112 Gbps SerDes demos by our SerDes IP partner, Credo, and the FlexE demo by several OEMs at the Optical Internetworking Forum (OIF) booth.
ESE: Was PAM4 a topic of much discussion at OFC?
KS: Yes, definitely. As I mentioned, the data rates and the demand on the data has been growing, so in order to support that demand, you need to have higher bandwidth on the line side. Several customers already have designs with 56 Gbps PAM4 SerDes, and designs with 112 Gbps PAM4 SerDes are under consideration.
SI: To add a bit more, for high speed SerDes 56 Gbps and beyond, you must go to PAM4, but PAM4 will have a higher bit error rate (BER) compared to NRZ SerDes. PAM4 is driving high data rates, and with forward error correction, one can achieve the same error rates as NRZ, yet get a better signal. For that reason, FEC has become a very important IP. FEC IP improves the bit error rate. Without FEC, the solution won’t work, because the error rates are high, and you would get a lossy channel, but with FEC IP, we can achieve a BER of <10-15, which is required by most standards.
ESE: What are the reasons Open-Silicon is in a good position to provide that corrective to the higher bit error rates one would otherwise encounter with the adoption of PAM4?
SI: Our Multi Channel Multi Rate (MCMR) FEC IP supports multiple channels and multiple rates. The configuration options that we provide allow the customers to fine tune for different applications and different requirements, so they do not need to worry about having to procure several FEC IPs for different use cases. They can configure the MCMR FEC IP for their application. The MCMR FEC IP supports bandwidths up to 400G with the ability to connect 16 SerDes lanes.
Multiple channel, multiple rate is very critical. That is where we believe we bring value to our customers: they get the most optimized FEC that supports multiple rates and multiple channels, with the lowest gate count, thus a more optimized area.
At the end of the day, we also must deliver the optimized custom SoC with all these IPs. So, we want to get the most optimal die size possible to keep the costs low; and we are in a great position to deliver that.