Open-Silicon .:. Solutions and Strategies to Mitigate the Physical Design, Assembly and Packaging Challenges of 2.5D ASIC SiPs
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Solutions and Strategies to Mitigate the Physical Design, Assembly and Packaging Challenges of 2.5D ASIC SiPs

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About the Webinar:

This Open-Silicon webinar, moderated by Herb Reiter of eda 2 asic Consulting, Inc., addressed the unique physical design, assembly and packaging challenges of 2.5D ASIC SiPs, and outlined the proven solutions and strategies that are available to mitigate these issues in order to successfully ramp ASIC SiP designs into volume production. Using a 2.5D HBM2 ASIC SiP as a case study, the panelists covered all aspects of physical design of the interposer, ASIC, signal integrity analysis and STA, rail analysis and power integrity analysis. They  also addressed the package design, assembly and testing both at the wafer level and the SiP level. The panelists emphasized the importance of understanding the entire 2.5D ASIC SiP manufacturing supply chain ecosystem and all of its stakeholders, such as the HBM2 memory, ASIC, interposer, package substrate, assembly house, foundry and more. Attendees learned about system planning, 2.5D ASIC SiP requirements and implementation strategies, package assembly flows, verification, test, and signoff. By understanding the implementation and manufacturing challenges associated with 2.5D ASIC SiPs and the solutions available, designers and architects are better equipped to achieve high volume manufacturing with lower risk, higher performance and faster time-to-market.

This webinar was ideal for chip designers and SoC architects of the next generation of high bandwidth applications in HPC, networking, deep learning, virtual reality, gaming, cloud computing and data centers.


Date: Tuesday, March 6, 2018
Time: 8 AM PST/ 11AM EST
Duration: 60 mins



Herb Reiter – Moderator
eda 2 asic Consulting, Inc.

After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb founded eda 2 asic Consulting in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role, Herb introduced innovative IC design tools to major semiconductor vendors worldwide and expanded his horizon to include interposers and 3D-ICs technology, semiconductor materials and manufacturing, metrology and test equipment. In his consulting role with the newly formed Electronic System Design Alliance (formerly known as EDAC) Herb drives their new System Scaling Working Group and a new edition of their Multi-die IC Design Guide. Herb is also contributing to the ESD Alliance’ focus to address important industry challenges together with ESD Alliance members from the IC Design community and IC Manufacturing companies, including their materials and equipment suppliers. Herb is also a frequent blogger, and has his own column (3D In Context) on the 3D InCites website.

Speaker Biographies:






Dan Leung
Director, Packaging & Assembly

Dan has over 30 years of experience in packaging and assembly, with nearly 20 of those years being at the director level. Prior to joining Open-Silicon in 2003, Dan served as Director, Assembly & Packaging for Lightspeed Semiconductor. Prior to that, he worked for Atmel Corp, Advanced Micro Devices and Monolithic Memories. Dan holds a bachelor’s degree in mechanical engineering from the University of California, Berkley.

Ashish Veeramaneni
Lead Design Engineer

As Design Lead at Open-Silicon, Ashish oversees ASIC and IP project teams working with cutting edge technologies, like 16nm, 14nm and 7nm, HBM IP development, 2.5D interposer design implementation and more. Prior to joining Open-Silicon, Ashish worked at Mediatek, Singapore and AMD, India as Physical Design Engineer. Ashish holds an MTech Degree in VLSI Design from NIT, Karnataka and a BTech degree in Electrical & Electronics Engineering from Kakatiya Institute of Technology, Warangal, India.

About Open-Silicon, Inc.

Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 135 million ASICs to date. To learn more, visit

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