Open-Silicon .:. SerDes Technology Center of Excellence
Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief


High Speed. Low Power. Smallest Possible Area. Easy Integration

SerDes (Serializer/DeSerializer) is a vital component for any data communication ASIC, with ever increasing bandwidth and speed requirements for enabling future technologies. Open-Silicon, a SiFive company, SerDes Technology Center of Excellence (Serdes TCoE) provides a one stop solution for designing high speed SerDes ASICs. Combined with the Open-Silicon’s OpenMODEL™  IP approach and vast experience of integrating SerDes in over 100+ ASICs, SerDes TCoE offers the best in class silicon proven SerDes solutions from its featured IP partners across nodes ranging down to 7nm, multiple foundries, protocols etc.

SerDes TCoE Offerings:

  • Channel Evaluation: Identify the right SerDes solution by evaluating the channels intended for the system
  • PCS and Controller Solutions: Evaluate the PCS and Controller/MAC requirements for the interface to the core and optimize for interoperability of hard and soft macros
  • Physical Integration: Evaluate the metal stack compatibility, special layer/Vt requirements, placement of SerDes on chip and bump plan for physical verification and packaging
  • Package/Board Design: collaborative work on packaging and board design including 3D parasitic extraction, Crosstalk/SSO/Noise Analysis and other system-level considerations
  • Silicon Bring-up: Close coordination with DFT and Test team for bring-up and quick assessment on ATE.

SerDes Protocols Supported:

  • PCI-Express (PCIe): Gen1, Gen2, Gen3, Gen4, Gen5
  • CEI-6G, 11G, 25G/28G, 56G, 112G
  • 10GBase-KR/KX4, 40GBase-KR4
  • JESD204B
  • Infiniband
  • Interlaken
  • SATA – rev 1, rev2, rev3 & SAS -12G

28Gbps SerDes Evaluation Platform:

SerDes Board

Open-Silicon’s 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development enabling rapid deployment of chips and systems for 100G networks,  includes a full board with packaged 28nm test chip, software and characterization data.  The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Rambus, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.

Target Applications and Markets

As part of the Open-Silicon SerDes Technology Center of Excellence (TcoE) offering, the 28G SerDes is targeted for ASIC and SoC deployment in high-data-rate, chip-to-chip and chip-to-module applications. Open-Silicon applies its unique, high-speed serial design expertise to ensure the successful delivery of ASICs and SoCs for next-generation, high-speed systems used in the networking, telecom, computing and storage markets.

Packaging and Availability

The 28-nm test chip designed in TSMC 28HPM has been packaged in a 19mm x 19mm, 324-ball high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate.  This package material was selected for its relatively wider trace characteristics, low loss tangent, and superior uniform via arrangements that minimize reflections in vertical transitions. Open-Silicon optimized the final package design through simulations to meet and exceed the guidance derived from the CEI specifications.

The snowPHY-C2 platform was developed in cooperation with Open-Silicon, Inc. Open-Silicon also developed a test board for measurements and characterization – Click here to read the Press Release by Semtech Corporation (Semtech is now Rambus)…

Want to get a budgetary quote for high-speed SerDes ASIC? Please fill out the Design Requirements Form.

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