A Methodology to Handle Increased Complexity
At 40nm and 28nm, lithographic limitations and atomistic doping greatly increase the burden on the design methodology. Variations are up, sensitivities are up, and at the same time the designs themselves are larger and encompass more building blocks than before. From a methodology point of view, focus areas like
signal integrity, power integrity, DFM and DFT all take on new complexities as a result. Open-Silicon’s 40nm and 28nm reference flows leverage the best in learning from Open-Silicon’s multiple EDA and foundry partners to put together a solution designed to meet Open-Silicon’s benchmark performance in terms of predictability and reliability.
Key among the issues that need to be managed are a greatly increased process variability, more complex timing behaviors, increased power density and switching currents, and increased layout dependent effects. For example, where power strapping might fix a dynamic IR power hot spot in 90nm, the same approach may be
insufficient for newer technologies. Also, variation imposes an increasing burden on device performance and power, and ultimately yield, requiring new approaches to deliver stable volume production. Open-Silicon’s methodology and technology teams would be happy to discuss with you our methodology in detail and help you understand how it could work for you on your design-specific challenges today.
Open-Silicon’s design engineering teams are experts in handling complex ASIC designs. Our disciplined approach combined with active feedback to customers throughout the design process ensures that programs are executed to a predictable design timetable. Our innovative design methodology combined with our deep design
expertise and experience in the selection, qualification and integration of third party IP, consistently delivers reliable silicon.
Early analysis of each customer’s design by our engineering team, including running Open-Silicon’s proprietary DesignScanner software, enables us to identify and resolve technical challenges even before the design is completed. Our rigorous and rigid design methodology then reduces any chances of design escapes, allowing us to deliver an industry-leading level of first-time silicon success.
Our OpenMODEL™ provides customers complete visibility into schedules and design issues. This fosters a collaborative approach to design. Full visibility regarding design, IP selection and integration helps customers make well informed decisions, which are invaluable for architectural and design trade-offs.
Five Phase Design Flow
Open-Silicon’s 5 phase design flow for standard netlist and RTL handoffs is shown below:
Five Step Physical Design Methodology
Open-Silicon’s standardized design methodology addresses the challenges of complex ASIC design in a disciplined manner to produce cost effective ASICs, with on-time schedules that are predictable and give reliable first silicon results.
Following the OpenMODEL™, our methodology is designed to target multiple process technologies at multiple foundries. It opens the design process to the customer allowing valuable customer feedback during the entire process. It follows a disciplined multiphase approach with clear entry and exit criteria, to identify and solve critical design challenges using industry standard tools and libraries that have been proven in several tape-outs across multiple manufacturing processes. The discipline, the checklists, and the distinct phases that are broken down to well-defined steps, help realize reliable first-silicon success.
Our design methodology is composed of 5 distinct phases:
- Analyze Phase
- Explore Phase
- Implement Phase
- Converge Phase
- Tape Out Phase
- Understand basic architecture requirements.
- Design planning, design parameter estimation.
- Identification of critical design challenges.
- Architecture, design requirements.
- Data flow diagram and/or paper floor-plan.
- Sample RTL / Netlist, timing constraints.
- List of memories and embedded IPs.
- DFT requirements.
- Package requirements, I/O plan, power requirements.
- All design collaterals in place (libraries, memory, I/P, run-sets etc.).
- Feedback on sample RTL/Netlist.
- Basic checks on die-size, power, metal layers done.
- Dry run the sample RTL/Netlist through tool flow for pipe cleaning.
- Sanity check on chosen package.
- DFT Physical implementation plan.
- Critical design challenges identified.
- Analyze phase checklist completed.
- Execute complete physical design process.
- Features, memories, and IP related macros are coded.
- Basic chip level logic verification is completed.
- Netlist meets Explore hand-off criteria.
- Full-chip netlist, Timing constraints.
- Basic timing, ATPG, physical & power models available for IPs.
- Top-level data flow diagram, paper floor plan, clock diagram.
- Floorplan & pad placement completed.
- Design placed & routed for feasibility.
- Block & chip-level timing analysis completed.
- Needed constraint refinements identified.
- Chip level setup timing performance within 10% of design requirements.
- Dry run the design through IR drop & SI analysis.
- DFT structures checked by customer.
- Input netlist verified against implemented netlist.
- Issues related to input netlist identified & fed back to customer.
- This is a trial tape-out phase.
- Complete all physical implementation tasks based on key learnings from Explore phase.
- Freeze design RTL, floorplan, chip-level ports, memory instances and macros.
- All architectural features are 100% coded and synthesized.
- Chip level logic verification run done
- Netlist meets Implement hand-off criteria.
- Full-chip netlist, timing constraints.
- Final timing, ATPG, physical & power models for IPs.
- Frozen clock architecture diagram
- Switching activity files.
- Floorplan, pad placement IO ring frozen.
- Design placed routed without congestion.
- Block chip-level timing analysis completed.
- Chip level setup & hold performance within 5% of design requirements.
- Chip level power SI requirements within 5 % of design requirements.
- DFT structures checked by customer; fault coverage meets design requirements.
- Dry run the design through physical verification flow.
- Input netlist formally verified against implemented netlist.
- Chip-level convergence for all performance attributes.
- Implement any customer ECOs.
- Entry criteria is the Implement phase closure.
- Completed Implement phase database.
- Full-chip ECO netlist (Netlist level ECOs only, no re-synthesis).
- Completed design layout.
- Power SI analysis completed with all fixes.
- Block chip-level setup & hold performance met.
- Full-chip gate-level simulation completed with timing (Customer).
- Scan, memBIST JTAG patterns simulation completed with timing.
- Physical verification run completed violations identified.
- Input netlist formally verified against implemented netlist.
Tape Out Phase
- Close on the physical database ship.
- GDSII to fab.
- Entry criteria is the Converge phase closure, no more ECOs.
- Physical data from Converge Phase.
- Clean design layout with all violations fixed.
- Physical verification flows run clean.
- Reliability (Power SI) checks run clean.
- All DFT related check completed.
- Tape-out paper work completed sent to foundry.
- Final GDSII data shipped to foundry.