Published by ChipEstimate.com
Many emerging networking and communications companies are looking for a well proven and cost effective ASIC solutions based on high speed SerDes interfaces. But design of an ASIC implementing these high speed SerDes interfaces-one that works successfully on a real board-is a huge challenge to system design teams. Accordingly, the ASIC designer must consider interactions beyond the chip level to ensure that the ASIC will function in its target environment. This article illustrates the full scope of these responsibilities. For successful integration of high speed SerDes, the challenges faced during various phases of die, package and board design are discussed. Each component has it’s own design requirements, but all need to be validated together to ensure correct performance at these frequencies. When high speed SerDes interface interacts strongly with the environment outside the device, it is prudent for the ASIC designer to consider interactions beyond the edges of the chip.
Case Study – High Speed. Low Power. Smallest Possible Area. Easy Integration –Integration of 28 Gbps SerDes for ASICs leveraging Open- Silicon’s TCoE (Technology Center of Excellence) SerDes TCoE Offerings:
Channel Evaluation: Identify the right SerDes solution by evaluating the channels intended for the system
PCS and Controller Solutions: Evaluate the PCS and Controller/MAC requirements for the interface to the core and optimize for interoperability of hard and soft macros
Physical Integration: Evaluate the metal stack compatibility, special layer/Vt requirements, placement of SerDes on chip and bump plan for physical verification and packaging
Package/Board Design: collaborative work on packaging and board design including 3D parasitic extraction, Crosstalk/SSO/Noise Analysis and other system-level considerations
Silicon Bring-up: Close coordination with DFT and Test team for bring-up and quick assessment on ATE.
While Open-Silicon’s SerDes TCoE offerings is quite extensive, this article will focus on challenges and solutions related to ASIC Package Design and System Board Design.
A device using four lanes of 28 Gbps SerDes is a powerful example. This article will cover the package selection, pin assignment, substrate and board routing considerations for a high-end 100G Ethernet/Backplane ASIC design. We will evaluate two package types for return loss, insertion loss, and crosstalk studies at the package level. At the PCB level, stack-up tradeoffs, surface roughness, routing, edge conditions, and loss implications will be covered. Actual results and simulated results will be compared.
ASIC Package Design Integrating 28Gbps SerDes
The 28nm SerDes was packaged with a high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate.
QUAD Bump & Ball Map Plan
– Bump Layout SerDes (Top)
– N and P pairs are behind each other (boxed) vertically. Adjacent columns are staggered at 180um
– RX (Light Blue), TX (yellow)
– There are VSS and VDDA bumps on the beachfront.
– 19mm x 19mm Ball Map
– Relevant Balls in SerDes ball area
– SerDes RX Pairs are on the outer 2 rows (light blue) at 1.0mm pitch
– A series of VDDA/VSSA balls separate the RX and TX balls
– TX balls are in the 4th and 5th rows (yellow)
– Other support balls (not shown) are in inside rows towards the die.
– Arrangement planned for low ball count in courtyard for future integrated product.
Design Implementation – 2 Materials compared
Summary for the 2 Material Options Considered
Results: 2 Material Techs compared – RX pair
Selected Package Characteristics & Summary Data
Routing example: RX
Post Design Data ; RX Characteristics 19mm x 19mm Package
Post Design Data ; TX Characteristics 19mm x 19mm Package
Power Supply for the QUAD
System Board Design – IL and RL target @ 28GHz
Impact of PCB Surface Roughness
PCB Stack-up Selection
TDR plot of TX lane (measured at break-out channel)
Eye opening of RX line when signal being looped back internally with PRBS7
Designing ASICs with high speed SerDes is becoming an increasingly complex task requiring competencies in several areas. Open-Silicon’s experience with integrating 28Gbps SerDes for ASICs combined with its comprehensive SerDes TCoE offering helps to overcome the challenges and implementation for the future networking and communication ASIC designs with next generation high speed 56Gbps SerDes.
Open-Silicon’s 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development enabling rapid deployment of chips and systems for 100G networks, includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech (now Rambus), and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.