Open-Silicon .:. Optimized ASIC Design Integrating High Speed SerDes
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Optimized ASIC Design Integrating High Speed SerDes

By: H. N. Naveen, Abu Eghan — Open-Silicon

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Many emerging networking and communications companies are looking for a well proven and cost effective ASIC solutions based on high speed SerDes interfaces. But design of an ASIC implementing these high speed SerDes interfaces-one that works successfully on a real board-is a huge challenge to system design teams. Accordingly, the ASIC designer must consider interactions beyond the chip level to ensure that the ASIC will function in its target environment. This article illustrates the full scope of these responsibilities. For successful integration of high speed SerDes, the challenges faced during various phases of die, package and board design are discussed.  Each component has it’s own design requirements, but all need to be validated together to ensure correct performance at these frequencies. When high speed SerDes interface interacts strongly with the environment outside the device, it is prudent for the ASIC designer to consider interactions beyond the edges of the chip.

Case Study – High Speed. Low Power. Smallest Possible Area. Easy Integration –Integration of 28 Gbps SerDes for ASICs leveraging Open- Silicon’s TCoE (Technology Center of Excellence) SerDes TCoE Offerings:

Channel Evaluation: Identify the right SerDes solution by evaluating the channels intended for the system

PCS and Controller Solutions: Evaluate the PCS and Controller/MAC requirements for the interface to the core and optimize for interoperability of hard and soft macros

Physical Integration: Evaluate the metal stack compatibility, special layer/Vt requirements, placement of SerDes on chip and bump plan for physical verification and packaging

Package/Board Design: collaborative work on packaging and board design including 3D parasitic extraction, Crosstalk/SSO/Noise Analysis and other system-level considerations

Silicon Bring-up: Close coordination with DFT and Test team for bring-up and quick assessment on ATE.

While Open-Silicon’s SerDes TCoE offerings is quite extensive, this article will focus on challenges and solutions related to ASIC Package Design and System Board Design.

A device using four lanes of 28 Gbps SerDes is a powerful example. This article will cover the package selection, pin assignment, substrate and board routing considerations for a high-end 100G Ethernet/Backplane ASIC design. We will evaluate two package types for return loss, insertion loss, and crosstalk studies at the package level. At the PCB level, stack-up tradeoffs, surface roughness, routing, edge conditions, and loss implications will be covered. Actual results and simulated results will be compared.

ASIC Package Design Integrating 28Gbps SerDes

The 28nm SerDes was packaged with a high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate.

  • The final package design was selected and optimized through simulations to meet targets culled from CEI specs – For example, pair to pair isolation better than -50dB, with substrate insertion loss of less than -1.0dB at 14GHz were achieved.
  • Attributes of the SerDes & Package
    • One Quad – 4 lanes was implemented with other GPIOs
    • Package size:19mm x 19mm with 324 balls at 1.0mm pitch
    • The 4 lanes and associated power balls occupied a quadrant of the package.
  • Main Drivers & Challenges:
    • High Performance and  Cost effective
    • High speed Signal handling capability over broad bandwidth
    • Escape and routing strategy including SerDes Ball Placement – for easy board break out as well as adequate isolation between channels
    • Package Technology selection – Looking for Consistency for fabricated product.
  • Guidelines on signals
  • Zdiff = 100 ohm
  • Zcomm = 25
  • Diff Insertion Loss: better than –1.5dB at  Nyquist (14.125GHz)
  • Summary of Other signal requirements  derived from CEI main standards (at right)
Open-Silicon Image 1

QUAD Bump & Ball Map Plan

– Bump Layout SerDes (Top)

– N and P pairs are behind each other (boxed) vertically. Adjacent columns are staggered at 180um

– RX (Light Blue), TX (yellow)

– There are VSS and VDDA bumps on the beachfront.

– 19mm x 19mm  Ball Map

– Relevant Balls in SerDes ball area

– SerDes RX Pairs are on the outer 2 rows (light blue)  at 1.0mm pitch

– A series of VDDA/VSSA balls separate the RX and TX balls

– TX balls are in the 4th and 5th rows (yellow)

– Other support balls (not shown) are in inside rows towards the die.

– Arrangement planned for low ball count in courtyard for future integrated product.

Open-Silicon Image 2

Design Implementation – 2 Materials compared

  • 2 Designs were implemented – one each per package technology type.
  • HiTCE escape – Bump
  • Bump plan required careful clearance of bumps before inner layer routing
  • Sideways escape plan to overcome tight pitch –  stripline (Top graphic).
  • High Density Build Up (HDBU)
  • Trace escape plan – lines between bumps. Were possible
  • The 2 package implementations were  compared  using HFSS extractions on
  • Insertion Loss
  • Return loss
  • Common mode losses


Open-Silicon Figure 3

Summary for the 2 Material Options Considered

figure 4.1

Results: 2 Material Techs compared –  RX pair

  • Results (No balls) – show the Insertion loss advantage for HiTCE. The  relatively quieter crosstalk environment  of HDBU is highlighted by the data.
  • SDD11 and SCC11 for both are highlighted.
figure 4


Selected Package Characteristics & Summary Data

  • 19×19 12-layer HiTCE.
    • This is a coreless package with less via transition losses.
    • There is also better impedance control consistency
    • Better overall insertion loss with wider traces, but some acceptable penalty for Crosstalk.
    • Coreless with uniform via for better return loss and common mode loss.
  • Key Material Prop – HiTCE GL773:
    • Er: 5.8 (10GHz)
    • Tan δ : 24e-4
    • σ: 3.33e+7 [S/m]
Image 5

Routing example: RX

  • RX trace pattern – These stripline traces were on layer 7 of 12 in the stack-up.
  • The traces highlight clearances around the bumps for easy sideways escape for improved return loss.
  • Similar stripline trace topology was used for the TX traces on layer 9 separated by VSSA plane.
  • The other traces in the graphic are general I/Os on the design
Image 6

Post Design Data ; RX Characteristics 19mm x 19mm Package

figure 7

Post Design Data ; TX Characteristics 19mm x 19mm Package

figure 8

Power Supply for the QUAD

  • Supplies for the Quad
  • These use common ground reference VSSA.
  • Low impedance Analog supply was targeted and achieved.
Open Silicon table 1
  • An optimized high bandwidth package design for 28Gbps was achieved with a high performance Low Temperature Co-Fired Ceramic (LTCC) material
  • Given the size and trace length requirements an alternate high density buildup (HDBU) package designs also met the same performance goals.
  • The LTCC version (HiTCE ceramic) was chosen by end customer to take advantage of the extra margins in the loss characteristics.
  • The resulting package was integrated into a test board. The full board with the package met all the test requirements without any issues.

System Board Design – IL and RL target @ 28GHz

  • Insertion Loss < -2 dB
  •  Return Loss  > -8 dB

Impact of PCB Surface Roughness

Open-Silicon Table 2
figure 9

PCB Stack-up Selection

figure 10


figure 11

Validation Board

figure 12

TDR plot of TX lane (measured at break-out channel)

image 13

Eye opening of RX line when signal being looped back internally with PRBS7

Designing ASICs with high speed SerDes is becoming an increasingly complex task requiring competencies in several areas. Open-Silicon’s experience with integrating 28Gbps SerDes for ASICs combined with its comprehensive SerDes TCoE offering helps to overcome the challenges and implementation for the future networking and communication ASIC designs with  next generation high speed 56Gbps SerDes.

Open-Silicon’s 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development enabling rapid deployment of chips and systems for 100G networks, includes a full board with packaged 28nm test chip, software and characterization data.  The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech (now Rambus), and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.

Click here to request for SerDes Evaluation Platform

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