MILPITAS, Calif., June 21, 2018 (GLOBE NEWSWIRE) — Open-Silicon, a system-optimized ASIC solution provider and long-standing member of TSMC’s Value Chain Aggregator (VCA) and Design Center Alliance (DCA) programs, will present on three topics at the TSMC Open Innovation Platform® (OIP) Theater at DAC 2018 in San Francisco. The presentations will address how increases in cores, bandwidth and data in deep learning and networking applications are driving the need for custom processors and ASIC SiPs with High Bandwidth Memory (HBM2). They will also provide an overview of the critical IP building blocks required for 2.5D HBM2 ASIC SiP design and manufacturing solutions.
All presentations will take place at the TSMC OIP Theater in Booth 1629.
- Who: Asim Salim, VP of Manufacturing Operations, Open-Silicon
What: Turnkey 2.5D HBM2 ASIC SiP Solution for Deep Learning and Networking Applications
This presentation will address the growing memory requirements for deep learning and networking applications, and how a silicon-proven HBM2 IP subsystem in TSMC’s FinFET and CoWoS® technologies is enabling these applications and successful ramping of 2.5D HBM2 ASIC SiP designs into volume production.
When: Monday, June 25, 2:15 – 2:30 p.m.
- Who: Kalpesh Sanghvi, Technical Manager for IP and Platforms, Open-Silicon
What: IP Subsystem Solutions for Deep Learning and Networking Applications
This presentation will address the key building blocks of deep learning and networking applications, including an HBM2 IP subsystem, a networking IP subsystem and a multi core processor IP subsystem including RISC-V targeted for TSMC’s advanced process technologies.
When: Tuesday, June 26, 11:30 – 11:45 a.m.
- Who: Abu Eghan, Sr. Manager of Packaging & Assembly Operations, Open-Silicon
What: Package Design, Assembly and Test Strategies for robust 2.5D HBM2 ASIC SiP Manufacturing
This presentation will address solutions and strategies for mitigating the interposer design, package design, assembly and test challenges associated with 2.5D HBM2 ASIC SiP manufacturing in TSMC’s FinFET and CoWoS® technologies.
When: Wednesday, June 27, 3:30 – 3:45 p.m.
When and Where:
On June 25, 26 & 27,
TSMC OIP Theater in Booth 1629,
Moscone Center West, San Francisco, CA
Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, visit www.open-silicon.com
Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.