Open-Silicon .:. Open-Silicon Showcases its 2.5D ASIC SiP Capabilities and Breadth of ASIC Solutions, Including its HBM2 IP Subsystem Solution and its Comprehensive Networking IP Subsystem Solution, at DesignCon 2018….
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Open-Silicon Showcases its 2.5D ASIC SiP Capabilities and Breadth of ASIC Solutions, Including its HBM2 IP Subsystem Solution and its Comprehensive Networking IP Subsystem Solution, at DesignCon 2018….

Open-Silicon, a system-optimized ASIC solutions provider, will be exhibiting at DesignCon 2018 in Santa Clara, CA on Jan. 31 and Feb. 1, 2018. The company will showcases its 2.5D ASIC SiP capabilities and breadth of ASIC Solutions, including its HBM2 IP Subsystem Solution and Comprehensive Networking IP Subsystem Solution.

Open-Silicon 2.5D ASIC SiP Capability – Multiple Know Good Die (KGD) attached to a single, passive silicon interposer with high density micro bumps enables connections between dice, as well as connections to the package substrate, using Through-Silicon Vias (TSVs) enabling 2.5D HBM2 ASIC SiPs. As an early advocate of 2.5D design technology and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling high bandwidth applications to leverage the HBM2 3D-stacked memories.

Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASIC SiPs in TSMC FinFET/CoWoS Technologies – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). The IP includes the controller, PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer. Open-Silicon’s HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high-bandwidth data transfer rates of >2Gbps, and interoperability between Open-Silicon’s HBM2 IP subsystem and HBM2 memory die-stack.

Comprehensive Networking IP Subsystem Solution Includes:

High Speed Chip-to-Chip Interface Interlaken IP – Open Silicon’s 8th generation Interlaken IP core supports up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high-bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.

Ethernet Physical Coding Sublayer (PCS) IP – Open-Silicon’s Ethernet PCS  IP core is compatible with various MII interfaces for connecting to the MAC and is uniquely built to work with off-the-shelf MAC and SerDes from leading technology vendors. It supports 64b/66b encoding/decoding for transmit and receive, and various data rates ranging from 10G to 400G. The Ethernet PCS IP complies with the IEEE 802.3 standard and supports Ethernet and Flex Ethernet interfaces, making it ideal for high-bandwidth Ethernet endpoint and Ethernet transport applications.

Flex Ethernet (FlexE) IP – Open-Silicon’s FlexE IP core features a generic mechanism that supports various Ethernet MAC rates, and is uniquely built to work with Open-Silicon’s packet interface and OTN client interface or off-the-shelf MACs. Open-Silicon’s FlexE IP is fully compliant to the OIF FlexE standard v1.0 and will be compliant to the upcoming v2.0. The IP supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network, making it ideal for high-bandwidth Ethernet transport applications.

Forward Error Correction (FEC) IP – Open-Silicon’s FEC IP core is capable of multi-channel multi-rate forward error correction in applications where the bit error rate is very high, such as high-speed SerDes 30G and above, and significantly improves bandwidth by enabling 56G PAM4 SerDes integration. This single-instance IP core is compatible with off-the-shelf SerDes from leading technology vendors and supports bandwidths up to 400G with the ability to connect 32 SerDes lanes. It can easily achieve a Bit Error Rate (BER) of <10 -15 with an input BER of <10 -6, which is required by most electrical interface standards using PAM4 SerDes. The FEC IP core supports the Interlaken and Ethernet standards, and significantly improves bandwidth by enabling high speed, multi-channel SerDes integration, making it ideal for high-bandwidth networking applications.

When: Jan 31 – Feb 1, 2018, 8am – 5:45pm
Where: Booth #1238, Santa Clara Convention Center, Santa Clara, CA

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 135 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, visit

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.