Open-Silicon .:. SiFive, Credo and Open-Silicon Showcase End-to-End Solutions for HPC and Networking Applications at SC18 in Dallas…
Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

SiFive, Credo and Open-Silicon Showcase End-to-End Solutions for HPC and Networking Applications at SC18 in Dallas…

SiFive, Credo and Open-Silicon will exhibit complete end-to-end solutions for HPC and networking applications at Supercomputing 2018 (SC18) in Dallas, TX. The co-demonstration illustrates the capabilities of SiFive’s highest performance RISC-V Core IP U7 Series, Open-Silicon’s HBM2 IP subsystem and Credo’s high performance, low power, mixed-signal 112Gbps PAM4 SerDes. Custom SoC solutions and critical IP cores, including Interlaken IP and Ethernet IP subsystems, will also be showcased.

The SiFive Core IP U7 Series is a high-performance RISC-V applications processor featuring a dual-issue superscalar core with domain-specific customizations required for embedding intelligence from the edge to the cloud. The U7 series microarchitecture optimizes performance and power enabling high throughput systems for diverse compute workloads and form-factors. Credo’s 112G SerDes, silicon proven in advanced 7nm FinFET node, enables rapid build-out of next-generation 100G, 400G and 800G Ethernet cloud networks, and delivers higher bandwidth, lower power and optimum lane count configurations. Open-Silicon’s HBM2 IP subsystem solution, in FinFET technologies, includes an HBM2 controller, PHY and interposer I/O. It provides the highest performance and flexibility for integrating HBM directly into next-generation custom SoC 2.5D SiP solutions.

Comprehensive Networking IP Subsystem Solution:

High Speed Chip-to-Chip Interface Interlaken IP – Open Silicon’s 8th generation Interlaken IP core supports up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high-bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.

Ethernet Physical Coding Sublayer (PCS) IP – Open-Silicon’s Ethernet PCS core is compatible with different MII interfaces for connecting to the MAC and is uniquely built to work with off-the-shelf MAC and SerDes from leading technology vendors. It supports 64b/66b encoding/decoding for transmit and receive, and various data rates, ranging from 10G to 400G. The Ethernet PCS IP complies with the IEEE 802.3 standard and supports Ethernet and Flex Ethernet interfaces, making it ideal for high-bandwidth Ethernet endpoint and Ethernet transport applications.

Flex Ethernet (FlexE) IP – Open-Silicon’s FlexE IP core features a generic mechanism that supports various Ethernet MAC rates, and is uniquely built to work with Open-Silicon’s packet interface and OTN client interface or off-the-shelf MACs. Open-Silicon’s FlexE IP is fully compliant to the OIF FlexE standard v1.0 and will be compliant to the upcoming v2.0. The IP supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network, making it ideal for high-bandwidth Ethernet transport applications.

Forward Error Correction (FEC) IP – Open-Silicon’s FEC IP core is capable of multi-channel multi-rate forward error correction in applications where the bit error rate is very high, such as high-speed SerDes 30G and above, and significantly improves bandwidth by enabling 56G PAM4 SerDes integration. This single-instance IP core is compatible with off-the-shelf SerDes from leading technology vendors and supports bandwidths up to 400G with the ability to connect 32 SerDes lanes. It can easily achieve a Bit Error Rate (BER) of <10-15 with an input BER of >10-6, which is required by most electrical interface standards using PAM4 SerDes. The FEC IP core supports the Interlaken and Ethernet standards, and significantly improves bandwidth by enabling high speed, multi-channel SerDes integration, making it ideal for high-bandwidth networking applications.

High Bandwidth Memory (HBM2) IP Subsystem Solution:

Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASIC SiPs in TSMC FinFET/CoWoS Technologies – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). The IP includes the controller, PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer. Open-Silicon’s HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high-bandwidth data transfer rates of >2Gbps, and interoperability between Open-Silicon’s HBM2 IP subsystem and HBM2 memory die-stack.

When: November 12-15, 2018

Where: Booth #406 – Kay Bailey Hutchison Convention Center, Dallas, TX

About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture.

About Credo
Credo is a leading provider of advanced SerDes IP.

About Open-Silicon
Open-Silicon, a SiFive company, is a system-optimized custom SoC solution provider.

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.