Want to get a budgetary quote for Interlaken ASIC? Please fill out the Design Requirements Form.
Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following
Interlaken Alliance specifications:
Designed and tested to be easily synthesizable into many ASIC technologies, the Open-Silicon Interlaken IP Core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.
Open-Silicon’s eighth-generation Interlaken IP core doubles user data bandwidth of the previous generation to 1.2 Tb/s by enhancing the SerDes and user interface support. This version of the IP core improves system reliability with the addition of Interlaken Retransmit Extension support. Building up on Open-Silicon’s robust and flexible architecture, the IP also adds support for multiple aggregate bandwidth interfaces within a single IP core instance, allowing for a more efficient implementation.
In addition to the key features highlighted with the latest release, the Open-Silicon Interlaken IP also provides the following feature set as part of the standard IP functionality:
For more information, please contact email@example.com
Visit Interlaken Alliance at www.interlakenalliance.com
Open-Silicon Unveils Industry’s Highest Performance Interlaken Chip-to-Chip Interface IP. www.marketwired.com
Open-Silicon’s Interlaken IP Core Selected for Netronome’s Next-Generation Flow Processors http://www.eeherald.com
Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products http://www.prnewswire.com
Open-Silicon’s Configurable Interlaken IP Core Delivers High-Performance Chip-to-Chip Interface for Networking Products at 28nm Process Node https://www.design-reuse.com
Open-Silicon’s Interlaken IP Core Chosen for ALAXALA’s Advanced Networking Infrastructure Device http://www.prnewswire.com
Open-Silicon Enhances its Interlaken IP Core For Very High-Speed Chip-to-Chip Serial Interfaces http://www.prnewswire.com
Open-Silicon Secures 20th Interlaken IP License http://alienness4.rssing.com