Open-Silicon .:. Open-Silicon IP Targets Networking
Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

Open-Silicon IP Targets Networking

MICROPROCESSOR report   –   Most Significant Bits

Open-Silicon IP Targets Networking

By Bob Wheeler,  December 12, 2017

Better known as an ASIC vendor, Open-Silicon is expanding its intellectual-property (IP) portfolio. It’s sup-plying new networking IP that eases chip integration for customers, even if they don’t use its ASIC services. Build-ing on its existing Interlaken core, the company announced IP cores for the Ethernet physical coding sublayer (PCS), for forward error correction (FEC), and for Flex Ethernet (FlexE). It also upgraded its Interlaken core to handle in-terfaces up to 1.2Tbps. The cores are available now for licensing or for use in new ASIC designs.
Open-Silicon’s customers prefer to remain anony-mous, but its ASIC customers include OEMs as well as chip vendors that sell ASSPs under their own brand. This approach allows the latter group to focus on architecture and front-end design while outsourcing physical design. Although resulting unit costs are higher than for a custom-er-owned-tooling (COT) model, an ASIC flow greatly re-duces in-house R&D expenses—generally a good financial tradeoff for low-volume products. On the OEM side, Open-Silicon typically serves smaller customers than ASIC leaders Broadcom and GlobalFoundries.
The company’s new PCS core handles Ethernet rates from 10Gbps to 400Gbps including the new 25Gbps, 50Gbps, and 200Gbps speeds. It performs multilane distri-bution (MLD), 64/66b encoding, scrambling, alignment-marker insertion/removal, and other functions between the MAC layer and the FEC interface. The new multichan-nel multirate (MCMR) FEC core supports both Ethernet and Interlaken. In the former case, it connects with the PCS core to complete the MAC-to-serdes data path, linking to as many as 32 serdes lanes. The MCMR FEC core handles Reed-Solomon FEC codes for various 802.3 clauses includ-ing the KP4 and KR4 variants of 802.3bj.
Open-Silicon’s new FlexE core is an optional block that logically sits between the Ethernet MACs and the PCS layer. FlexE is an Optical Internetworking Forum (OIF) specifica-tion that allows more-granular Ethernet link rates. It allows MAC rates that are either greater than the underlying PHY rate (through bonding) or less than the PHY rate. The FlexE core is essentially a sophisticated multiplexer (or gearbox) that handles MAC rates from 10Gbps to 400Gbps and adapts them to 100Gbps PCS lanes. We view FlexE as pri-marily serving data-center interconnects (DCIs), where it enables optimum utilization of optical bandwidth.
The latest Interlaken core is what Open-Silicon calls its eighth-generation design. Enhancements include sup-port for 56Gbps serdes rates, interfaces up to 1.2Tbps, and optional FEC (using the MCMR FEC core). The ASIC-side interface is user configurable to widths of 128, 256, or 512 bits. The core can perform simultaneous in-band and out-of-band flow control.
The Interlaken Alliance specified optional Reed-Solomon FEC in an extension published in December 2016. It added this feature to handle faster serdes rates, particu-larly the OIF’s CEI-56G-MR-PAM4 and other PAM4-based 56Gbps implementations. Adding FEC leaves the Interlaken protocol unchanged, as the new function sits between the framing layer and the serdes lanes. In the data path, Interlaken connects packet processors to OTN fram-er/mappers on the line side and switch fabrics on the sys-tem side.
Separately, Open-Silicon has delivered a High Band-width Memory 2 (HBM2) solution, which includes con-troller and PHY IP. For ASIC customers, it procures the HBM2 memory die from Samsung or SK Hynix and delivers packaged and tested 2.5D chips. Although it developed the HBM2 core primarily for high-performance-computing customers, about one-third of the company’s engage-ments come from networking customers. We see HBM2 solving the memory-bandwidth problem in packet pro-cessors that implement deep buffers, which would oth-erwise be constrained by the pin count of external GDDR or DDR4 memory channels.
The notable omission in Open-Silicon’s offering, rela-tive to Broadcom’s and GlobalFoundries’, is 56Gbps PAM4 serdes. For 28Gbps NRZ serdes, the company worked with the Snowbush IP group at Semtech to validate the latter’s design in silicon. In 2016, Semtech divested that group to Rambus, which subsequently announced it was working with GlobalFoundries and Samsung for 56Gbps serdes IP. Open-Silicon is collaborating with other third-party ven-dors to provide a 56Gbps solution, but it has yet to an-nounce a partner. For now, this situation forces Open-Silicon customers that are using TSMC to rely on either Broadcom—a competitor—or smaller IP providers such as Credo Semiconductor (see MPR 2/8/17, “Credo Goes ASSP With PAM4 PHY”).
With its new Interlaken, FlexE, and FEC cores, Open-Silicon is providing IP that isn’t widely available from third parties. Also, it can customize these blocks to meet the spe-cific requirements of customer designs. Offering IP cores enables it to engage customers early in their design cycles, often leading to ASIC business. The expanded networking IP benefits customers by allowing them to focus on prod-uct differentiation rather than “recreating the wheel” by implementing standard blocks.

© The Linley Group  •  Microprocessor Report, December 2017