Open-Silicon .:. Manufacturing
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World-Class Partners

Open-Silicon partners with world-class foundries to provide complete manufacturing services. Our staff brings years of semiconductor manufacturing experience and product engineering expertise to every engagement.

We work closely with our customer to identify and select the right process and technology solution for each design. Selecting the process node and the optimal process options requires careful comparison between different foundries, design objectives, market applications and target price. Our manufacturing experts pride themselves in staying current with all existing and emerging process technologies to ensure complete choice through our OpenMODEL™.

Throughout each stage of manufacturing our foundry manager will monitor all activities in the fab once engineering and production lots are started. We provide split lot and wafer staging capabilities to our customer. The fab WIP will be easily accessible to our customer through our web based tracking system ASICView. Our product engineering group will track and monitor the PCM data to ensure the wafers are within the spec and use this data later on to correlate to the final yield.

Best-In-Class Production Controls

Open-Silicon’s experienced Production Control (PC) team plays a crucial role once the customer releases their part to production. This team performs and monitors the following activities to guarantee on-time delivery:

  • Scheduling, planning and forecasting
  • Wafer, assembly and test management
  • Inventory management
  • 24×7 automated WIP tracking and reporting via ASICView
  • Shipments tracking

We internally measure several metrics and share them with our customers. These include:

  • OTD – On-Time Delivery
  • OSD – Original Schedule Date
  • CRD – Customer Request Date
  • Lead times
  • OTD to OSD
  • OTD to CRD
  • RMA response time

Through our continuous improvement efforts, we provide regular feedback to the foundries as part of the yield enhancement program. We also provide our customers with FIT numbers on regular processes to further ensure the quality of their product.

Test Engineering

A Complete Test Engineering Solution

Open-Silicon views test engineering as an essential part of the design process, so we address test very early in the design cycle. Our test engineers have extensive design for testability (DFT) experience with a variety of automatic test equipment (ATE). This allows us to create a smooth transition from a simulation environment to a tester environment, thus avoiding getting stuck in endless loops while debugging test vectors.

Open-Silicon’s test engineering capabilities include:

  • Ultra low-cost digital test
  • High-performance digital test including high speed interfaces
  • Analog and mixed-signal test
  • RF test

Test – A Holistic View

Open-Silicon views test engineering as an essential part of the design process so we address test very early in the design cycle. Our test engineers have experience in both DFT and ATE equipment. This allows us to create a smooth transition from simulation environment to tester environment, thus avoiding the endless loop of debugging test vectors.

We work with multiple vendors and have experience with several test platforms. In addition to traditional ATPG, advanced DFT techniques such as memory and logic built-in self-test (BIST) and boundary scan are part of our normal test flow.

We work closely with our customers to perform any special functional vectors that may be required and provide vectors
guidelines and test vector playback capabilities which minimize tester debugging time and saves the customer money. We also provide our customers with a test plan that will satisfy fault coverage requirements.

Open-Silicon’s experienced engineers will determine the most cost-effective production tester based on the required pin count, speed, and nature of the design.

Collaboration for Best Results

Open-Silicon works with multiple on shore and off shore vendors to gain the benefits of fast local device test bring-up and ultra-low production costs.  Open-Silicon also has a team in Kaohsiung, Taiwan, to directly support the offshoring of test programs for high-volume production.  The test engineering team has experience with several test platforms. In addition to traditional ATPG, advanced DFT techniques such as memory and logic built-in self-test (BIST) and boundary scan are also part of our normal test flow.

We work closely with our customers to perform any special functional vectors that may be required and provide vectors guidelines and test vector playback capabilities which minimize tester debugging time and save customer money. We also provide our customers with a test plan that will satisfy fault coverage requirements.  Open-Silicon’s experienced engineers will determine the most cost-effective production tester based on the required pin count, speed, and nature of the design.

Package Engineering

A Complete Solution

Open-Silicon provides a complete solution, from package selection, through design & development and into high-volume manufacturing. We understand the importance of selecting the proper packaging solution to meet the technical and cost constraints of each design. Our packaging capabilities are very broad and our experience level very deep to meet the unique needs of each customer to successfully launch their product into any of the following:

  1. Wafer-level chip scale packages
  2. Low-cost leadframe packages
  3. The full range of BGA packages
  4. High-performance flip chip packages
  5. Organic and ceramic packaging
  6. Multi-Chip Packages, including both stacked and side-by-side die configurations
  7. Signal and power integrity modeling of packages and PCBs
  8. High-performance interface design, including >10GHz SerDes, high speed DDR2/3, and WiMAX

Working Together

The OpenMODEL™ allows our customers complete visibility and flexibility in designing the optimal package solution. Our package engineers engage very early in the design cycle, in order to collaborate with our customers in evaluating the most optimum package solution based on their specific design and application requirements. We also work closely with the IC physical design engineers to make sure the substrate design will meet the product specifications.

The package engineering role does not end at the substrate design. We provide a preliminary thermal analysis to check the power requirement and final package model parameters. We also work closely with our customers to evaluate any PCB design, manufacturability, environmental and reliability (1st & 2nd Level) requirements and issues. Our close collaboration with our partners enables us to vertically link up all activities in the manufacturing value chain and provide our customers with full access to documents such as bonding diagrams and substrate design documents as well as assembly WIP through our online program management system, ASICVIEW.


Open-Silicon Quality Policy

It is the policy of Open-Silicon to supply products that meet or exceed customer requirements and expectations with high quality and on-time delivery. To this end, Open-Silicon will:

  • Develop an exemplary understanding of our customer’s product requirements
  • Measure our internal success through the use of departmental objectives that monitor and identify areas for continual improvement in all business activities
  • Measure our external success through the satisfaction of our customers

It is through continual improvement in our processes that we will achieve the goal of increasing customer satisfaction while making it easier for our customers.

Open-Silicon Quality Policy
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ISO 9001:2015 Certification

The International Organization for Standards (ISO) is the largest standards organization in the world, with a network of
standards institutes from 159 countries. The ISO 9001 is a set of procedures covering all key processes within a business and ensures that these processes are efficient, effective and are monitored consistently allowing the company to continuously improve on its processes.

ISO 9000 is a family of standards for Quality Management Systems that was updated to the ISO 9001:2015 on April 23, 2018.

Open-Silicon ISO 9001-2008
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Multi-Layer Masks

Reduces Mask Costs by Up to 50% for 90nm and Smaller Lithographies

Until now, complete choice for every step in the process of designing and manufacturing a custom ASIC has not been fully realized. The OpenMODEL™ revolutionizes the ASIC supply chain by allowing customers to be involved in the supply chain choices that not only reduce costs, but dramatically improve the chances of right-first-time silicon.

Mask costs have received a lot of attention as a primary factor in the rising cost of ASICs. Many companies have tried to address rising mask cost concerns by creating platforms that predefine the metal layers. Multi-layer masks are the first solution that offers a cost-saving option for customers who need a full custom ASIC to differentiate their products in the market.

Multi Layer Mask
Multi-layer masks reduce total mask cost by writing multiple mask layers of the same mask grade onto one reticle.

Multi Layer Mask

Multi-layer masks are particularly cost-effective for companies that need low or medium volumes at 90nm or smaller processes nodes.


Yield Enhancement

Maximum Yield

The primary goal of Open-Silicon’s Product Engineering Group is to maximize the yield of chips from each wafer produced. We monitor yields on regular basis and work closely with both the foundry engineers and the assembly house to address any process drift or changes that may cause yield issues.

As part of the debug process, we perform failure analysis upon any Return Material Request (RMA) and issue 8 Discipline (8D) reports explaining the root cause of the problem and the corrective actions that need to be taken to avoid the problem in the future. We also perform product characterization at different process splits and operating conditions in order to guarantee the quality of the product. Our team assists customers during the validation and debugging phase by providing bench measurement and FIB work if required.

Open-Silicon provides a full suite of die and package qualification including burn-in, ESD, latch up, and Highly Accelerated Stress Test (HAST). We also have the capability of performing second level reliability testing.

Failure Analysis

State-of-the-Art Capabilities

Open-Silicon utilizes the latest equipment for silicon failure analysis, including:

  • E-Beam Microscopes
  • Scanning Electron Microscopes (SEM)
  • Focused Ion Beam (FIB) including Dual Beam
  • Emission Microscopes
  • Liquid Crystal Hot Spot Detection
  • X-Ray Imaging Systems
  • Scanning Acoustic Microscopes
  • Ball Shear and PULL Testers
  • Wire Pull Testers
  • Laser Markers
  • High Power Microscope Decapping Systems
  • Plasma Etchers
  • Atomic Microscopes

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