Location: Bangalore, India.
Minimum Educational Qualifications: B.Tech/Master’s degree in electronics
Relevant Experience: 4 – 7 years
No of Opening: 2
Job Description: Lead physical design and physical design verification tasks across the various projects.
Own project specific flow setup and maintenance.
Physical design tasks include floor-planning, place and route, CTS, timing closure, IR analysis and LEC for block level, full chip flat and hierarchical designs. Co-ordinate the full chip physical design and verification activities.
Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database. This also includes DFM checks for the advanced node designs.
Ensure correct IP and pad-ring integration in block and flat designs.
Prepare training plan and conduct training of new PD/PDV team members, new tools flow set-up and any tool evaluations.
Responsible for the projects running with the team members and guide them on technical issues if people responsibilities are attached.
Ensure Check list items are followed / Verified within projects.
Please mention ‘Job Title’ and ‘Location’ in the subject line of your mail and mail your Resume along with ‘Cover Letter’ to careers.india@open-Silicon.com
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