15+ years of experience
Bachelors / Masters Degree in Engineering
• Play a leadership role in managing the development of Interface and Analog IPs for internal ASIC or external customers
• Hands on experience of Hard analog or PHY blocks on circuit design in latest finfet nodes like 16nm and 7nm
• Mentoring and leading the team in terms of BKM
• Work with Sales, Marketing and PM teams across globe to drive the processes for solid IP Development methodology to ensure success with customers
• Ability to support multiple customers and IP Deliveries
• Strong knowledge in all aspects of integration of IP related to e.g. logic design and verification, physical design, packaging, test and characterization. experience in the IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous experience in DDR, HBM, SerDes is preferred.
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