Date: Tuesday, September 19, 2017
Time: 8 AM PDT/11AM EDT
This Open-Silicon webinar, moderated by Herb Reiter of eda 2 asic Consulting, Inc., provided an overview HBM2 ASIC SiPs (System in a Package) for density and bandwidth-hungry systems based on silicon proven Open-Silicon’s High Bandwidth Memory (HBM2) IP subsystem solution. Attendees also learned about the system integration aspects of 2.5D HBM ASIC SiP, and performance results of various memory access patterns suiting different applications in High Performance Computing and Networking. The webinar also summarized silicon validation results of a 2.5D HBM2 ASIC SiP validation/evaluation platform, which is based on Open-Silicon’s HBM2 IP subsystem in TSMC’s 16nm in combination with TSMC’s CoWoSTM 2.5D silicon- interposer technology and HBM2 memory. They discussed the significance of the results and how they demonstrate functional validation and interoperability between Open-Silicon’s HBM2 IP subsystem and the HBM2 memory die stack. Attendees learned about HBM2 memory and its advantages, applications and use cases. The panelists also discussed the HBM2 IP subsystem roadmap and Open-Silicon’s next generation multi-port AXI (Advanced eXtensible Interface) based HBM2 IP subsystem development targeting 2.4Gbps per-pin data rates, and beyond, in TSMC’s 7nm technology.
Webinar focus audience:
This webinar was designed to address the queries of chip designers and system architects of emerging applications, such as high performance computing, networking, deep learning, neural networks, virtual reality, gaming, cloud computing and data centers.
Herb Reiter – Moderator
Eda 2 asic Consulting, Inc.
After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb founded eda 2 asic Consulting in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role, Herb introduced innovative IC design tools to major semiconductor vendors worldwide and expanded his horizon to include interposers and 3D-ICs technology, semiconductor materials and manufacturing, metrology and test equipment. In his consulting role with the newly formed Electronic System Design Alliance (formerly known as EDAC) Herb drives their new System Scaling Working Group and a new edition of their Multi-die IC Design Guide. Herb is also contributing to the ESD Alliance’ focus to address important industry challenges together with ESD Alliance members from the IC Design community and IC Manufacturing companies, including their materials and equipment suppliers. Herb is also a frequent blogger, and has his own column (3D In Context) on the 3D InCites website.
Technical Sales Manager IP & Platforms
Kalpesh is responsible for business development and technical pre-sales/support for IP and platforms. He has over a decade of professional experience in the semiconductor and embedded industry. Kalpesh has in-depth knowledge of software development and bring-up for SoC/ASIC designs, and domain expertise in IoT, storage solutions, security solutions, networking and multimedia reference designs. He is also experienced in ASIC design flows, pre-silicon and post-silicon bring-up and validation as well as prototyping solutions. Prior to joining Open-Silicon, Kalpesh held engineering positions at Pace plc and Sasken Communication Technologies Ltd. Kalpesh holds a Bachelor of Engineering degree in Computers from the University of Pune in India.
Vinay serves as a Principal Architect at Open-Silicon, where he is responsible for IP and SoC development. He has nearly two decades of experience in SoC architecture, design engineering, IP and a wide variety of protocols. Prior to joining Open-Silicon, Vinay held engineering positions at Broadcom Limited, Cisco, Conexant Systems and Synopsys. He holds a Bachelor of Engineering degree in Electronics & Telecommunications for Goa University in India.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
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