Date: Thursday, December 7, 2017
Time: 8 AM PST/ 11AM EST
This Open-Silicon webinar, moderated by Eric Esteve of SemiWiki, addressed the benefits of the multi-channel multi-rate forward error correction (MCMR FEC) IP and the role it plays in high-bandwidth networking applications, especially those where the bit error rate is very high, such as high speed SerDes 30G and above. The panelists outlined the challenges that applications designers of high-bandwidth networking applications encounter, such as support for various protocols, integration and compatibility with various high speed SerDes supporting different widths, and different rate and channel requirements. They outlined use cases and discussed the key technical advantages that the MCMR FEC IP core offers, such as support for up to 56Gbps SerDes integration, bandwidth of up to 400G, support for KP4 RS (544,514) and KR4 RS (528,514), support for Interlaken, Flex Ethernet and 802.3x protocols, support for configurable alignment marker, and PRBS test pattern generator and loopback test. The panelists also discussed the architectural advantages of the core, such as its flexibility, configurability and scalability, all of which enable the MCMR FEC IP to be uniquely tailored to address customer specific application requirements. The MCMR FEC IP is part of Open-Silicon’s networking IP portfolio that includes the company’s Interlaken IP core, as well as its new Ethernet PCS and Flex Ethernet IPs, which enable high-bandwidth chip-to-chip, Ethernet endpoint and Ethernet transport applications.
Webinar focus audience:
This webinar was specifically designed for chip designers and SoC architects of high-speed, high-performance communication and computing applications such as packet processing/NPU, traffic management, switch fabric, switch fabric interface, Framer/Mapper, TCAMs, Serial Memory, FPGA and more.
Eric Esteve – Moderator
Eric serves as Design IP and SC Technology Blogger for SemiWiki where he focuses on design IP, ASIC and SoC technology, verification IP, SC strategy and IP marketing. He has 20 years of expertise in ASICs, and an additional ten years of experience in IP design. Eric is also the owner of IPnest, a consulting and writing firm that publishes the Interface IP Survey and DESIGN IP Report. He holds a PhD in Physics of Semiconductor from Pierre and Marie Curie University in Paris, and he earned a Diplôme d’études appliquées (DEA) in microelectronics from Université Paris Diderot.
Technical Sales Manager IP & Platforms
Kalpesh is responsible for business development and technical pre-sales/support for IP and platforms. He has over a decade of professional experience in the semiconductor and embedded industry. Kalpesh has in-depth knowledge of software development and bring-up for SoC/ASIC designs, and domain expertise in IoT, storage solutions, security solutions, networking and multimedia reference designs. He is also experienced in ASIC design flows, pre-silicon and post-silicon bring-up and validation as well as prototyping solutions. Prior to joining Open-Silicon, Kalpesh held engineering positions at Pace plc and Sasken Communication Technologies Ltd. Kalpesh holds a Bachelor of Engineering degree in Computers from the University of Pune in India.
Engineering Manager, IP and SoC Development
Davendra serves as Engineering Manager for IP and SoC for Open-Silicon, where he is responsible for IP and SoC development. He has 15 years of experience in engineering. Prior to joining Open-Silicon, Davendra held engineering positions in Tokyo, Japan at tata elxsi, NETWORK PROGRAMS KK and Softbridge Solutions. Prior to that he was a design engineer for Proton Electronics in Pune, India. Davendra holds a post graduate diploma in VLSI from CDAC, Pune and a Bachelor of Engineering degree in Electronics and Telecom from the University of Pune in India.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
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