President & CEO-Open-Silicon
The biggest challenge the semi-conductor industry faces today is slowing innovation. Although Silicon Valley is full of gifted designers, the levels of innovation in the industry are nowhere near what they were 15 years ago. Since the process for developing and executing new ideas is becoming more lengthy and capital intensive, industry growth has decelerated to half its long-term growth average since 2010.
To address this problem we must re-examine our business models and the constraint expensive designs placed on product innovation. The risk we run with inordinate costs is shrinking the market to a point where it becomes prohibitive to try new things. For example, design starts have not graduated from 28nm to 16nm as quickly as anticipated and now companies are forced to consider compromises like spending $1.5M at 130nm to try a new idea because a 16nm design could cost up to $50M. Instead of pursuing the best design, many in Silicon Valley are opting for the safest. In response to this trend, companies like Open-Silicon are modifying industry design flows and business models to reduce the prodigious time and capital investments that go into new designs.
Holistic Design and ASIC Partners
The best strategy for lowering expenses without compromising product integrity is by rethinking the industry approach to design. Traditionally the majority of front-end design happens in-house and outside vendors handle physical design and manufacturing. The problem with this model is that the overall success of the chip’s design is dependent on everything that happens during front-end design. Ideally, companies should take a holistic approach that anticipates back-end challenges from the beginning. With a holistic approach and careful consideration of each design phase, designers can reduce costs and avoid the usual design setbacks by addressing problems when the cost of error is lower.
Understanding chip design phases is just as important as strategically selecting design partners with the appropriate expertise. A partner with the right experience could complete designs faster with a higher probability of first-pass silicon success. By reducing the number of respins you could ultimately reduce the cost of the design by 30 percent to 40 percent. It is crucial to capitalize on the efficiencies companies have developed over many years of completing various designs for different applications. Experienced designers provide valuable guidance regarding which IP or protocol will work best and where to take a risk and where not to take a risk.
The call for quicker, cost-effective designs is what prompted Open-Silicon to establish a Technology Center of Excellence (TCoE) for complex IP subsystems like High- Speed SerDes & ARM CPU Cores. These holistic centers improve time-to-market and design quality with access to world-class front-end and back-end design capabilities, IP integration, and packaging and test services. The TCoE allows Open-Silicon to engage with customers at every level of design and address their challenges holistically, ensuring they meet their power, performance, and timeto- market goals. With the expertise that comes with 300+ ASIC design tape-outs and 100M+ ASIC shipments, we can guarantee the successful delivery of affordable ASICs.
New Developments to Reduce Costs
Experienced designers with the right resources are finding other ways to produce less expensive designs. One solution that we’ve invested in at Open-Silicon is 2.5D and 3D stacking. 2.5D and 3D stacking creates ways to mix and match chip-components meaning products can be divided into multiple dies so that some functions can be at a less expensive process mode, mixed with other functions that require a high frequency or new low power technique. Although 2.5D and 3D stacking may not be the solution for every complex SoC design, it is a customizable option with a lower cost of development.
Another expense saving design option that Open- Silicon offers is virtual prototyping. Traditional prototyping methods require major development efforts and are expensive to replicate. The key benefits for an alternative or complementary virtual prototype are faster time-to-software-development, improved software quality, and lower development costs. In the last few years virtual prototyping has become a mainstream part of SoC design. Companies who invest in the right virtual prototyping tool are finding that they can quickly develop fully functional virtual prototypes with moderate effort. Consequently, software quality is improving because virtual prototyping systems allow more lengthy automated software testing.
Encouraging Silicon Innovation
The responsibility of companies like Open-Silicon is to facilitate advances in semi-conductor technology. In an industry dependent on continuous innovation, we can’t allow costs to keep us from pursuing the development of more complex architectures. There are enough visionary designers and industry newcomers with innovative ideas that could change the world. Our job is to reduce the risk of trying something new so that they can translate their ideas into real platforms. By understanding and streamlining the design process and partnering with companies who have years of design and manufacturing experience, I am confident the industry can again rise to the innovation levels of the early 2000s.
President & CEO-Open-Silicon