“We are offering 3D memory stacks integrated into the ASIC package using silicon interposer 2.5D technology,” Hans Bouwmeester, vice president of IP and Engineering Operations at Open-Silicon told EE Times in an exclusive interview. “The result is higher performance, lower power and a smaller form factor–a three way win.”
Anyone with an ASIC idea can improve its access to memory–especially compared with DDR version four (DDR4)–by applying Open-Silicon’s HBM SiP approach including the necessary IP and using JEDEC-compliant HBM memory chips, which come in stacked-die 3D versions.
Open-Silicon uses an interposer that allows 1,024-bit parallel paths to connect the memory to the ASIC in extremely close proximity for bandwidth that rivals putting the memory on the ASIC die itself, but without the expense and low yields that would otherwise result.
Yields are high because “we only put pretested known-good ASICs onto the interposer with pretested known good 3D HBM memory die stacks in our SiPs, making yields very high,” Bouwmeester told EE Times.
The customer gets the advantage of using their own custom logic, while Open-Silicon provides all the HBM IP for putting their ASIC together with JEDEC-compliant HBM memory chips. Most of Open-Silicon’s customers with bandwidth and power constrained systems are in high-performance computing, networking, high-end consumer, and graphics applications all of which will be benefit from HBM ASIC SiP, according to the company.
— R. Colin Johnson, Advanced Technology Editor, EE Times