Open-Silicon .:. asic requirement document
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ASIC Requirements Document (ARD)

Open-Silicon Inc.

490 N. McCarthy, Suite 220, Milpitas, CA 95035

This document is used to obtain all the required information to create an ASIC Proposal & Quote to the customer for the given Project.
User guidelines:
1. Where required please tick the box
2. Select, is a pulldown menu

Customer info

Your First Name*
Your Last Name*
Your Work Email*
PIN Code/ZIP Code*

1. Product info :

  (Description of application of ASIC)

2. Product Volume and Target Price:

2018 2019 2020 2021 2022 2023
Volume :
Target Price :

3.Design Handoff:

4.Requested Schedule:

Vendor selection :
Open-Silicon RTL design start, if needed :
Final Netlist handoff :
Final RTL handoff :
Tapeout date :
Initial protos target :
Volume production target :

5. Technical Details:

Process Variation (e.g. LP) No. of Layers
Process (node and metal layers) :
Core Voltage (v) : Tech_Det_Process
Special requirements : Embedded Flash : id:Technical_EmbeddedFlash
RDL : Tech_Det_Rdl
Multi-VT : Details :
1T-SRAM / eDRAM : Tech_Det_Sram
Mixed Signal Layers : DNW Ultra Thick Metal Ploy R MIM
Efuse : Tech_Det_Efuse
Other :
Gate Count (including FFs) : Check if DFT ovrhd is incl.
Amount of embedded memory (Mb) :
Expected Die Size : X (mm) = Y (mm) =
Die Size : X (mm) = Y (mm) =
Fastest Core Clock (MHz) :
Number of FFs :

6. Internal SRAMs:

SRAM Name RAM type (1rw, 1r1w, 2rw, 2r2w,ROM, TCAM, EEPROM, eFlash) Depth Width # of instances Total bits
Total Embedded Memory :

7. IP Requirements:

Name Type (Hard / Soft) # of instances Description Is Gate count included
in Section 8?
Origin (customer,
Open-Silicon, or IP vendor)

6. I/Os:

8. I/Os:

IO Name & Type Check if
# of Inputs # of O/P & Bidir SSO P/G Freq Voltage
Total Signal IOs : Core P/G IOs :
Total IOs : Total P/G IOs :

7. Package:

9. Package:

Total expected power dissipation (W) :
Ambient Temp. Range (Commercial: 70C,Industrial: 85C) :
Junction Temperature (Tj in DegC) :
Airflow, if any (m/s) :
Is it OK to use heat sink? : Package_isitok
Type (BGA, FC, etc) Pins Body Size Height Ball/pin pitch
Pb-free, ROHS, or Green requirement, if any :

8. Test Requirements:

  (scan, mBIST and JTAG are required by default)

10. Test Requirements:

  (scan, mBIST and JTAG are required by default)

Will customer provide scan inserted RTL/Netlist? : Test_Requir_willcustomer
Functional Vectors : Are Functional Vectors needed? : Test_Requir_arefunctional
If so, expected # of vectors. :
Any special testing requirements (pls. provide details) :
Is production burn-in required? : Test_Requir_isproduction

9. Additional Requirements:

11. Additional Requirements: