Open-Silicon .:. Custom SoC Design
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Want to get a budgetary quote for Custom SoC Design? Please fill out the Design Requirements Form.

Derivatives and Spec Handoff (Turnkey) Designs

With derivative SoC designs, a company’s core product team focuses on future roadmap development while leveraging an engineering partner to extend existing SoC development investment to meet market needs and derivative market opportunities. With spec handoff designs, Open-Silicon leverages it’s deep experience in Networking, Telecom, Storage, and Computing to take the lead in defining the SoC architecture and system design.

Spec Handoff

The starting point for a custom SoC can be an idea, concept, block diagram or specification.  Open-Silicon’s technical solutions managers will work with the customer to review the available industry expertise and technology and select the best solution for each program.  Then, Open-Silicon’s experienced systems engineers will work with customer to develop a full product plan including a microarchitecture specification suitable for RTL design and design verification.  From that point, Open-Silicon’s program manager will provide a single point of ownership for all actions, managing the project through Open-Silicon’s ASICView program management software.

Open-Silicon’s teams have strong vertical expertise that enables them to make the right decisions for customers to minimize the amount of customer engineering needed to fully develop a new semiconductor product. From a detailed design flow and process, and a commitment to complete documentation, to a rigorous system of checklists, customer’s can trust Open-Silicon to put quality first and execute to their satisfaction.

Custom SoC Design

Open-Silicon’s roots are in custom silicon design, including both RTL and Netlist handoffs.  Open-Silicon continues to expand its ASIC offerings, including more IP partners, optimal foundry technology choice, and in-house technology solutions to design the best possible custom silicon.

Disciplined Methodology

Open-Silicon’s design engineering teams are experts in handling complex ASIC designs, with the experience of over 10 20 million gate designs under our belts. Our disciplined approach, combines active feedback to customers throughout the design process and ensures that programs are executed to a predictable design timetable. Our innovative design methodology, combined with our deep design expertise and experience in the selection, qualification and integration of third party IP, enables the consistent delivery of reliable silicon.

Early analysis of each customer’s design by our engineering team, including running Open-Silicon’s in-house developed DesignScanner software, allows us to identify and resolve technical challenges even before the design is completed. Our rigorous and rigid design methodology then reduces any chances of design escapes, allowing us to deliver an industry-leading level of first-time silicon success.  Over two thirds of Open-Silicon’s new design starts come from repeat customers.

Our OpenMODEL™ provides customers complete visibility into schedules and design issues. This fosters a collaborative approach to design. Full visibility regarding design, IP selection and integration helps customers make well-informed decisions, which are invaluable for architectural and design trade-offs.


What is Design-Lite?

The semiconductor industry moved to a fab-lite model previously to focus on product development. The current industry transition,called design-lite, will allow customers to develop expanded product lines with current engineering staff by leveraging partners like Open-Silicon to build derivative products. With derivative SoCs, a company’s internal engineering team designs a core design, and then variations to that, called derivatives, are designed and manufactured by Open-Silicon. This allows customers to add revenue to an existing IC product line through modifications to that design without pulling the engineering team from its next generation core product roadmap focus. The net result is a greater return on the overall product line investment.

Why is it the trend?

The cost of semiconductor product development continues to grow, yet companies have limited finances for product line investment.Time-to-market pressures  remain high, with design cycles getting shorter and market-driven product requirements increasing.

As investment budgets are smaller, the number of design teams internally have shrunk and yet need to produce more product revenue. Companies need to extend the life and use of their product roadmaps to meet financial requirements. Finally, companies are finding growth through smaller marketing addressed with “customized ICs” to meet that specific market’s needs.

Case Study:

Situation: An Open-Silicon customer developed a video processing chip for a personal media player. This product was a part of the core product roadmap, however the company knew there was potential revenue that was being missed with video processing chips in other markets.

Problem: The company was constrained due to headcount and resources and needed to keep its team working on the next generation of its product.

Solution: Working with Open-Silicon, the customer indentified four secondary video processing chip markets:

  1. Security, which required high-end resolutions
  2. Digital camera/GPS, which required power/audio and language capability
  3. Video MP3, focused on high resolution and cost
  4. Cellular, with photo/power and cost requirements met

For this development, the customer allocated a full-time architect and a part-time program manager to manage coordination of the internal resources.  Open-Silicon took in the prior generation design RTL as a starting point and updated that design to match the new market requirements, including shrinking the design a couple technology nodes to reduce cost and power.Open-Silicon also managed the software driver design and evaluation board designs to maximize the customer’s leverage in getting these new products to market.

Networking Telecom Storage

Networking, Telecom, and Storage Design Experience

Extensive design experience with networking products such as Router Traffic Managers and Fabrics.

Architecture and Implementation

  • 10G & 40G router Fabric Chipset
  • Traffic Management Chipsets

Designs have included features such as:

  • Cell-based Switch Fabrics (Segmentation/Reassembly)
  • Virtual Output Queuing
  • Paged Memory Management, Thresholds, Watermarks
  • Classification, Policing, Congestion Analysis
  • RED, QOS, Traffic Shaping
  • Networking Interfaces (Interlaken, SPI-4, CSIX, etc…)
  • Memory Interfaces (ZBT, QDR, SDRAM, FCRAM, DDR2, DDR3)

Networking IP

  • Interlaken
  • SPI-4 Phase 2
  • PCI 2.2
  • Floating Point Units


Server and High Performance Computing Design Experience

Senior design team with extensive high-end computing design experience:

  • Extensive high bandwidth balanced system design capability
  • High performance scalar and vector design
  • Fixed and floating-point design
  • Memory architecture and design
  • Multiprocessor interconnect architecture/design
  • Supercomputer Experience-Cray 1, 2, 3, XMP, YMP, C90, T90, T3d, T3E, J90, SV1, X1-IBM, SST, ETA, Control Data, Prisma, Convex, Unisys
  • Most recent design: Supercomputer-55 Million gates-Custom 5G SERDES

Computing IP

  • PCI 2.2
  • Floating Point Units
Want to get a budgetary quote for Custom SoC Design? Please fill out the Design Requirements Form.