Date: Tuesday, June 13, 2017
Time: 8:00 AM PST
This Open-Silicon webinar, moderated by Eric Esteve of SemiWiki, addressed the benefits of the Interlaken high-speed chip-to-chip interface IP, and the role it plays in very high-bandwidth chip-to-chip communication applications. There are significant demands for performance and bandwidth in high-speed communications, and pressure to step up the pace on technological advancements. The panelists outlined the challenges that designers of advanced communication applications encounter with things like controller specification, latency, various SerDes architectures and implementation. They outlined use cases and discussed the key technical advantages that the Interlaken IP core offers, such as 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC), as well is its multiple user-data interface options. They also discussed the architectural advantages of the core, such as its flexibility, configurability and scalability.
Webinar focus audience:
This webinar was designed to address the queries of chip designers and architects of high-speed, high-performance communication and computing products such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications and any other high-end communication, networking and data processing applications.
Eric Esteve – Moderator
Eric serves as Design IP and SC Technology Blogger for SemiWiki where he focuses on design IP, ASIC and SoC technology, verification IP, SC strategy and IP marketing. He has 20 years of expertise in ASICs, and an additional ten years of experience in IP design. Eric is also the owner of IPnest, a consulting and writing firm that publishes the Interface IP Survey and DESIGN IP Report. He holds a PhD in Physics of Semiconductor from Pierre and Marie Curie University in Paris, and he earned a Diplôme d’études appliquées (DEA) in microelectronics from Université Paris Diderot.
Technical Sales Manager IP & Platforms
Kalpesh is responsible for business development and technical pre-sales/support for IP and platforms. He has over a decade of professional experience in the semiconductor and embedded industry. Kalpesh has in-depth knowledge of software development and bring-up for SoC/ASIC designs, and domain expertise in IoT, storage solutions, security solutions, networking and multimedia reference designs. He is also experienced in ASIC design flows, pre-silicon and post-silicon bring-up and validation as well as prototyping solutions. Prior to joining Open-Silicon, Kalpesh held engineering positions at Pace plc and Sasken Communication Technologies Ltd. Kalpesh holds a Bachelor of Engineering degree in Computers from the University of Pune in India.
Engineering Manager, IP and SoC Development
Davendra serves as Engineering Manager for IP and SoC for Open-Silicon, where he is responsible for IP and SoC development. He has 15 years of experience in engineering. Prior to joining Open-Silicon, Davendra held engineering positions in Tokyo, Japan at tata elxsi, NETWORK PROGRAMS KK and Softbridge Solutions. Prior to that he was a design engineer for Proton Electronics in Pune, India. Davendra holds a post graduate diploma in VLSI from CDAC, Pune and a Bachelor of Engineering degree in Electronics and Telecom from the University of Pune in India.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
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