2.5D IC is a packaging technology where multiple die are placed face down and side by side on a silicon or organic interposer. The active surface of the die has micro-bumps which connect to pads on the surface of the silicon interposer. Connections from these pads, directly connect to TSVs (Through Silicon Vias) which pass through the interposer substrate and connect to the package substrate. The connections from the pads can also be connected through interposer routing to other TSVs that are in-turn connected to pads and micro-bumps of other die on the interposer. 2.5D IC technology helps reduce interconnection length between multiple dies assembled on interposer leading to lower power consumption and lower latency as well as increase the number of interconnection routes on the interposer which results in increased bandwidth compared to traditional 2D off-chip interconnections.
The picture above shows mounting 2 or more silicon dies onto an interposer die and then assembling the whole system into a single package.
Silicon’s based on 2.5D technology are making inroads into high performance computing, graphic processors, AI (Artificial Intelligence) processors utilizing High Bandwidth Memories (HBM). These High Bandwidth Memories are available as tested KGDs (Known Good Die) are mounted on interposer along with die containing main processor and HBM controller. High density routing through the interposer interconnects the two die.
The main advantages of this technology are miniaturization, enhanced performance, lower latency, increased bandwidth and power efficiency. Key advantage of 2.5D technology is that the die that are mounted on interposer need not utilize same process node or technology. This helps in using die manufactured in various technology nodes. As an example, a HBM 3D stacked memory die can be mounted on the interposer with a processor die manufactured in 7nm process technology.
Open-Silicon’s HBM2 (High Bandwidth Memory) IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high bandwidth data transfer and interoperability between Open-Silicon’s HBM2 IP subsystem and HBM2 memory die-stack.
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