Happy 10th Anniversary to Open-Silicon!

Open-Silicon is celebrating another birthday! It has been 10 years since Open-Silicon began serving the semiconductor community here in the Silicon Valley and around the globe.


Comprehensive Capabilities

Open-Silicon offers comprehensive system design capabilities to our customers:

System Design

Industry-Leading Experience

Open-Silicon engineers have been designing electronic systems, large and small, for over 15 years. Whether your system is a large stand alone system or a sub-component of a larger assembly, our engineers can help you create the perfect combination of form and function.  In addition, Open-Silicon continues to use an existing network of industry-leading design services partners, managed by Open-Silicon’s Program Managers, to offer customers the best fitting design solutions on the market.

Available individually or as full turnkey solutions, the electronic system design services include:

Architectural Considerations

  • Partitioning
  • Memory and I/O bandwidth requirements
  • Chip interconnect protocol requirements

System Design

  • Memory subsystem
  • Maintenance subsystem
  • Clock distribution

System-Level Signal Integrity Analysis

  • Interconnect modeling using HSPICE (xtalk, attenuation, ISI, etc.)
  • Reflections
  • SSO analysis

Global Engineering

Eau Claire, Wisconsin

Reinforcing its commitment to customer needs, Open-Silicon acquired Silicon Logic Engineering (SLE) in Eau Claire, Wisconsin, in 2009 to enhance the company’s derivative IC design capabilities. SLE was founded in 1996 from senior engineers formerly with supercomputer company Cray Research.  Over the past 13 years, Silicon Logic Engineering has provided the ASIC industry with architecture, RTL design, design verification, and physical design services and grown to a respected industry icon with a reputation as the premier design center for highly complex designs. With an average of more than 20 years of engineering experience on designs up to 50M+ gates, SLE’s team brings extensive technical knowledge of the computing, networking, telecommunications and military/aerospace industries.

Raleigh, North Carolina

In 2010, Open-Silicon opened an office in the Research Triangle Park (RTP), centrally located between Raleigh, Chapel Hill and Durham, North Carolina, to meet the increasing demand for derivative SoC solutions. Located near cutting edge universities and several large technology companies, the center provides Open-Silicon with an additional global facility
to support its growing customer base with experienced system design engineers.

Milpitas, California

The Milpitas corporate headquarters, centrally located in Silicon Valley, provides package and test engineering, IP support and production engineering. In addition the customer program management and quality teams are based in Milpitas. These teams work closely with customers, partners, and other Open-Silicon global facilities to deliver the best custom silicon solutions.

Bangalore, India

Open-Silicon’s physical design center in Bangalore, India, also includes systems engineering.  In addition to the growing in-house Bangalore systems engineering capability, the Bangalore team also works with Open-Silicon’s design partners based in India to offer the best-fitting solutions.

Pune, India

Open-Silicon opened the Pune system design center in 2010 in response to continued global demand for derivative design collaboration. With derivative SoCs, a company’s internal engineering team designs a core product, and then variations to that design, called derivatives, are designed and manufactured by Open-Silicon. This allows Open-Silicon’s customers to address many more markets than it could with its original product alone. Open-Silicon continues to expand its engineering team in vertical markets such as networking, telecom, storage and computing to meet customer demand.

Think Physical

Design Process

Open-Silicon’s Think Physical™ design process allows Open-Silicon’s team to accurately predict the effects that back-end processes have on physical design closure. Combining the team’s experience, knowledge, and databases, the engineers plan for these effects from the beginning, and implement the design to prevent or minimize the effects’ impact on physical design closure. The process continues to evolve with today’s latest technologies and EDA design tools and has become a new standard approach for right-first-time complex ASIC designs.

Open-Silicon’s Think Physical design process is more than a methodology – it’s a philosophy. To some, the process is counter-intuitive, since too often the first thing a team of engineers plan to do is write RTL. The process is slightly different for FPGA design versus ASIC design, but the philosophy and some of the techniques remain the same.

Think Physical ASIC process advocates that design teams start by outlining the entire design flow, from architecture all the way through to tape-out, before any code is written. This allows all the team members to understand how the specific constraints of the architecture, the technology, the verification environment, the synthesis flow, and the place & route flow mutually interact and affect the tasks associated with each group on the team. As a result of the early planning, the overall system and design process is streamlined and design closure is easier to achieve.

Open-Silicon’s Think Physical design process has its roots in the supercomputer industry, where high performance, large gate count ASICs have been the norm for years. The concepts inherent within the process have evolved as technology has improved. Today, Open-Silicon’s engineers take advantage of the latest EDA tools and focus their energy on finding solutions to the new problems associated with today’s deep-submicron CMOS technologies.

While the process is evolutionary, the results are revolutionary- designs that work!

If you have questions about Open-Silicon’s Think Physical design process, please contact us.

Design Verification

Verification Approach

Test Environments and Simulation

  • Synopsys VMM & RVM
  • Cadence eRM & OVM
  • SystemVerilog, Verilog, Specman e and Vera HVL/HDL expertise
  • Self-checking simulations
  • Automated regression management

Methodology and Testing

  • Coverage-driven, constrained random methodology
  • Functional and code coverage tracking and reporting
  • Verification plan / checklist creation and annotation
  • Transaction-based testing
  • Constrained-random testing
  • Directed testing

SystemVerilog Assertions (SVA)

  • Testbench
  • Interfaces
  • Embedded in RTL

Behavioral and performance modeling

  • C/C++, SystemC, SystemVerilog, Verilog, Specman e, Vera
  • Performance testing

Logical Equivalence Checking (LEC)

  • Synopsys Formality, Cadence Conformal

Formal verification

  • Synopsys Magellan