ARM TechCon

Visit with Open-Silicon at ARM TechCon and learn about our ARM Center of Excellence.

Booth #8

October 25, 2011

Santa Clara Convention Center

5001 Great America Parkway

Santa Clara, CA 95054

Presentation: “Efficient Clock Tree Analysis and Implementation for UDSM Nodes SoCs” by Seshagiri Yalavarthy and Raju Rakha of Open-Silicon

When: Wednesday, October 19, 2011, 12:00 – 12:30 p.m.
Where: Room: Vijayanagar II at Vivanta by Taj in Bangalore, India

Presentation: “SI ‘Prevention and Optimization’ Flow for Clock and Signal Nets in UDSM Designs” by Jwalant Trivedi of Open-Silicon, and Tirendra Kumar of Cadence
When: Wednesday, October 19, 2011, 2:00 – 2:30 p.m.
Where: Room: Vijayanagar II at Vivanta by Taj in Bangalore, India

Visit with Open-Silicon and learn about our
latest technology and partnership news at the
TSMC OIP Ecosystem Forum

Tuesday, October 18, 2011

San Jose McEnery Convention Center

150 West San Carlos St

San Jose, CA 95113

Presentation: “Addressing the physical challenges and improving predictability using RC- Physical” by Tilak Miryala of Open-Silicon
When: Thursday, October 13, 2011 at 2:30 – 3:05 p.m.
Where: Room: C at the Pan Pacific Yokohama Bay Hotel Tokyu, in Yokohama, Japan

Open-Silicon to Discuss Semiconductor Design and Advanced Process Nodes at Global Technology Conference 2011

Santa Clara Convention Center, Santa Clara, CA

Tuesday, August 30, 2011

Panel: Time For a Mainstream Revolution
Location: Santa Clara Convention Center, Theater
When: Tuesday, August 30, 2011 at 4:30 p.m. – 5:30 p.m.
Moderator: Ed Sperling, Editor in Chief - System-Level Design
Panelists: Dr. Naveed Sherwani - Open-Silicon, Inc.; John Heinlein, VP Marketing - PIPD, ARM; Walter Ng, VP IP Ecosystem - GLOBALFOUNDRIES; Vishal Kapoor, VP Marketing - SoC Realization, Cadence

Presentation: Global Semiconductor Ecosystems Evolution
Location: Santa Clara Convention Center, Santa Clara, CA in Hall B
When: Tuesday, August 30, 2011 at 5:00 p.m.
Presenter: Colin Baldwin, Director of Marketing

Exhibit
Santa Clara Convention Center, Santa Clara, CA
Exhibit hall channel partners section, booth #C403

Open-Silicon to Discuss Evolution of Supply Chain at SEMICON West

Moscone Center, San Francisco, CA

Design and Manufacturing Panel: Stacking Effects: A Look at How the Global Supply Chain Will Change in 2.5D and 3D

When: Tuesday, July 12, 2011, 10:40 am
Location: NorthTwo TechXPOT

Session Summary: The promise of stacked die has enormous implications for the global semiconductor industry, from design all the way through to packaging and manufacturing. Can this work in a disaggregated industry involving IP from multiple vendors, multiple development tools, different process technologies and companies that have never had to work together in the past?

Moderated by Ed Sperling of SemiMD, Mr. Colin Baldwin of Open-Silicon will be joined by other senior-level executives from Mentor Graphics, eSilicon, Tessera, and Qualcomm.

Open-Silicon to Present at DAC 2011

San Diego Convention Center, CA

Date: Tuesday, June 7, 2011 and Wednesday, June 8, 2011

DAC Management Day

Time: 10:30 am- 12:00 pm

Location: 32AB

Dr. Naveed Sherwani, Open-Silicon's president and CEO will present on various trends at play in today's semiconductor marketplace.

Synopsys' Conversation Central

Time: 2:00 pm-2:30 pm

Location: Synopsys' booth #3433

Dr. Naveed Sherwani, Open-Silicon's president and CEO will discuss with other industry leaders top issues facing the industry.

Chipestimate.com IP Talks!

Time: 3:00 pm-3:30 pm

Location: Chipestimate's booth, #1731

Dr. Naveed Sherwani, Open-Silicon's president and CEO will discuss how third party IP has enabled growth and greater ROI in the semidonductor industry.

User Track Session 6 - Poster Session #2

Wednesday, June 8, 2011

Time: 1:00-2:00 PM

Location: Outside Room 33ABC

Anusha Gudla of Open-Silicon will present on "A Novel Cost-Effective Approach for Accurate Early Power Network Synthesis for Power-Gated SoCs"

Meet with Open-Silicon at Israel's largest semiconductor conference, ChipEx

Date: May 4, 2011
Booth: #09
Location: Hilton Tel Aviv Convention Center, Tel Aviv, Israel

Open-Silicon to Discuss Global Supply Chain Issues at the Israel Executive Forum

When: 5:30 PM, Tuesday, May 3, 2011
Where: Hilton Tel Aviv, Tel Aviv, Israel

Panel Summary:
During a panel moderated by Marvell, executives from Open-Silicon, GigOptix, STMicroelectronics, and ISE labs will discuss during a panel session "Operations the Right Way-Working through the Challenges of Global Supply Chain Management".

Open-Silicon to present “Moving Toward Design-Lite for Innovation” at the Design And Reuse IP-SoC Days

When: Tuesday, April 26, 2011 at 9:00 a.m.
Where: Hilton Santa Clara, 4949 Great America Parkway, Santa Clara, CA 95054

Presentation Summary:

Dr. Naveed Sherwani, president and CEO of Open-Silicon, will examine the evolution of the EDA industry, from the adoption of third party IP for complex designs, to fab-lite, where chip fabrication was outsourced to specialized manufacturers, and now the current industry transition to the design-lite model. While innovation requirements coexist with time-to-market pressures, companies are seeking new ways to maximize the return on their product investments. Design-lite enables a company’s engineering team to focus on the core product roadmap, while utilizing the design capabilities of another company to build derivatives of those products and expand market reach. Not only is the market ready for design-lite model, it is necessary in order to meet today’s various design challenges.

Visit Open-Silicon at TSMC Technology Symposium Boston

Tuesday, April 12, 2011
Time: 8:00am-3:45pm
Location: The Westin Hotel- Waltham Boston, 70 Third Ave., Waltham, MA 02451

Visit Open-Silicon at TSMC Technology Symposium San Jose

Tuesday, April 5, 2011
Time: 8:00am-6:30pm
Location: San Jose McEnery Convention Center, 408 S. Almaden Blvd. San Jose, CA 95110

Enter to win a new Sony TX9 digital still camera at the booth!

Visit Open-Silicon at SNUG San Jose

Monday, March 28th, 2011
Time: 4:30-7:30pm
Location: Hall B
Booth: 609

Open-Silicon will be in the IP section of the floor to talk about our experience integrating Synopsys IP as the first partner of Synopsys' OEM IP Partner Program.  This Expo event, run by SNUG, is open to all SNUG San Jose registered attendees.

Other Open-Silicon IP partners, including ARM, ChipEstimate.com will also exhibit in this section of the show.

Open-Silicon CEO to Present at SEMICON China

Open-Silicon, president and CEO, Dr. Naveed Sherwani, will present at the SEMICON China “IC Design to Manufacturing Conference,” sponsored by CASPA, SICA and Zhangjiang. Dr. Sherwani’s presentation will examine China’s key role in the global semiconductor market, and its shift from integrator to designer and manufacturer. He will address the key components of success, and China’s unique position to excel in semiconductor development and production.

What: Presentation:
“China and the Global Semiconductor Market”

When/Where:
SEMICON China: Thursday, March 17, 2011, 3:00 p.m. – Function Room 1, Kerry Hotel Pudong, Shanghai

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Open-Silicon CEO to Present at China Semiconductor Industry & Technology Forum

Open-Silicon's president and CEO, Dr. Naveed Sherwani, will present “China and the Global Semiconductor Market” at the “Zhangjiang Semiconductor Technology and Industrial Forum,” sponsored by CASPA, SICA and Zhangjiang. Dr. Sherwani’s presentation will examine China’s key role in the global semiconductor market, and its shift from integrator to designer and manufacturer. He will address the key components of success, and China’s unique position to excel in semiconductor development and production.

What:
Presentation: “China and the Global Semiconductor Market”

When/Where:
Zhangjiang Semiconductor Technology and Industrial Forum: Wednesday, March 16, 2011, 10:50 a.m. – 2nd Floor, Bldg. 16, Block C, No. 1387, Zhangdong Road, Shanghai

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Open-Silicon to Deliver Technical Presentation At DATE 2011 in France

MILPITAS, Calif. – March 9, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that Mr. Taher Madraswala, VP of engineering for Open-Silicon, will participate in a special executive session at Design, Automation & Test in Europe (DATE) in Grenoble, France.

Mr. Madraswala will present “Ideas on EDA and IP Convergence” during an executive session about today’s EDA and IP industries and the upcoming challenges they face. Moderated by Peggy Aycinena of EDA Confidential, Mr. Madraswala will be joined by other senior-level executives from Atrenta, ARM, Cadence, Infineon and Synopsys.

Session Overview: Designing today's emerging chips necessitates advanced methods and flows, which include the utilization of a coherent set of IP blocks and interoperable EDA tools. This impacts today’s IP and EDA industries and results in new solutions based on technical and business alliances and convergence. This session will discuss the above topic and address the upcoming challenges.

Location: Oisans Room, Alpexpo, Avenue d’Innsbruck, Grenoble, France

Date/Time: Tuesday, March 15, 2011, 11:30 a.m.

Open-Silicon’s Taher Madraswala to Deliver Keynote Address at CDNLive! India

Open-Silicon, Inc., vice president of engineering, Taher Madraswala, will be the guest keynote speaker at CDNLive! India. In addition the company will deliver presentations in four separate technical sessions about the implementations, challenges and solutions associated with complex SoC design. Open-Silicon will have a booth in the Designer Expo to talk about its recent 2.4Ghz MIPS processor design and senior functional manager, Shrikrishna Mehetre will be one of judges for the best paper selection in the Digital IC track and engineering manager Prashant Shrivastava will act as one of the judges for the best paper selection in the Silicon Realization: Verification & FED track.

What:
· Presentation: “Challenges and Solutions With the Clock Tree Implementation of Complex Networking Chips” by Jwalant Trivedi, senior ASIC design engineer, and Sudarshan Nagabhushanrao, senior ASIC design

· Presentation: “High-Performance FCBGA Design, Implementation & Challenges” by Kavitha Nagarajan, senior package engineer, and Gopinathan Balakrishnan, lead package assembly engineer

· Presentation: “Encountering ‘State of the Art’ SoCs with Accurate Planning to Quick Convergence” by Raju Rakha, senior ASIC design engineer, Derrick Joseph, senior ASIC design engineer, and Prasan Shanbhag, ASIC design engineer

· Presentation: “Predictable Debugging Using Interactive Short Locator for SoC Designs” by Sukumar Bandi, ASIC design engineer, and Ravi Bagewadi, lead ASIC design engineer

When:
Tuesday, November 16, 2010, 8:45 a.m. - 6:45 p.m.

Where:
ITC Royal Gardenia Hotel, Bangalore, India

EDA360 In the Real World Panel

Tuesday, October 26, 2010
11:00 am PDT
Fairmont Hotel, San Jose, CA

Naveed Sherwani, CEO of Open-Silicon will participate on a panel discussing issues facing the semiconductor industry around cost of silicon, increase of software content, design-lite approach to design

Moderator: Vishal Kapoor, Vice President, Product Management, New Businesses
Vice President, Strategic Business Alliances, Cadence

Panelists: ARM, Common Platform, GLOBALFOUNDRIES, and Open-Silicon

“Future Platforms of Computing: Moving Toward Design-Lite for Innovation”

Saturday, October 23, 2010, 1:45 p.m. - 5:15 p.m. PDT

Santa Clara Convention Center, Santa Clara, CA

Moderator: Liang Peng, CASPA BoD; Platform Architect, Intel

Panelists: Kamwar Chadha, Chief Marketing Officer, CSR
Co-founder of Sirf Bryon Shaw, Managing Director of Advanced Technology, General Motors
Dr. Naveed Sherwani, Co-Founder, President & Chief Executive Officer, Open-Silicon, Inc.

Abstract: The discussion, “Moving Toward Design-Lite for Innovation” will address planning for the future of not only the electronics industry, but the entire global economy, including strategies for reducing our carbon footprint. Companies must take a holistic approach and consider their impact across the entire product life cycle. There are many points across a design, from architecture level to production level, where optimization for low power can happen. Meanwhile, the industry is moving toward optical interfaces to enable higher bandwidth. While innovation requirements coexist with time-to-market pressures, companies are seeking new ways to maximize the return on their product investments. One of these strategies includes Design-lite. Design-lite enables a company’s engineering team to focus on the core product roadmap, while utilizing the design capabilities of another company, like Open-Silicon, to build derivatives of those products.

“IP/SOC Ecosystem for Today’s Complex Designs and Advanced Technology”

Friday, October 8, 2010, 1:30 p.m. - 2:30 p.m. PST

Santa Clara Convention Center, Santa Clara, CA

Moderator: Wen Huang, Vice President, Corporate Marketing, SMIC

Panelists: Mahesh Tirupattur, Executive Vice President, Analog Bits
Dr. Dipesh Patel, Vice President, Engineering, ARM
Brian Gardner, Group Director, Cadence
Dr. Naveed Sherwani, Co-Founder, President & Chief Executive Officer, Open-Silicon, Inc.
Navraj Nandra, Senior Director, Marketing, Synopsys
Dr. Wayne Dai, Chairman & CEO, VeriSilicon

Panel Abstract: The panel, “IP/SOC Ecosystems for Today’s Complex Designs and Advanced Technology,” will address licensed IP from IP vendors versus design service parties, and the pros and cons for each model; IP interoperability versus migration and how customers can benefit from the interoperability between foundries during the migration from current technology to advanced technology; the tradeoff in IP platforms versus subsystems and the choices customers are faced with; the IP forecast down the road and the role of EDA, design services and foundries, as well as the hurdles for advanced technologies; and IP identification and protection and the standards and implementations associated with these.