Over 30 Interlaken IP Implementations Demonstrate Flexibility and Reliability

MILPITAS, Calif. – January 23, 2012: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and charter member of the Interlaken Alliance, announced today that the company’s Interlaken IP core has been used in over thirty implementations, and now includes silicon success in 28nm. The five generations of Open-Silicon Interlaken Controller IP have delivered to the market the high-performance necessary for leading networking devices. This scalable IP core offers a low risk solution that is proven across multiple foundries and process nodes. Open-Silicon’s Interlaken IP, available as a standalone third-party IP core or as part of a customizable system and physical design solution, provides customers a quicker path to silicon.

According to a recently published report from Global Industry Analysts, Inc. (GIA), the information technology and communications (ICT) networking equipment/products market is expected to reach $214.2 billion by 2015. The market has been fuelled by the insatiable demand for bandwidth driven by multi-media applications, multiple users sharing a network, and more advanced PCs. Having recognized this trend early on, Open-Silicon developed the Interlaken IP core that has now been silicon proven in some of the most advanced process nodes.

“We found that our customers needed high-performance networking interface IP that was not available on the open market. Using our deep experience in integrating semiconductor IP, we developed the easiest-to-integrate ASIC Interlaken IP core with the highest-bandwidth for customers creating advanced networking products,” said Aashish Malhotra, director of IP solutions, Open-Silicon. “As the Interlaken protocol has evolved to address additional applications, so has our IP core. We believe that offering the lowest risk solution, that meets the Interlaken Alliance’s released specification will allow the industry to make a smooth transition to 100Gbps applications and beyond.”

About the ASIC Interlaken IP Core
Developed to incorporate of the benefits of the popular SPI4.2 and XUAI interfaces, Interlaken is a scalable protocol for chip-to-chip packet transfers. High–bandwidth applications, such as those required in networking devices, can utilize the Interlaken protocol to build on the channelization and per channel flow control features of SPI4.2, while also reduce the number of chip I/O pins by using high-speed SerDes technology. Interlaken as a protocol had transitioned from the original chip to chip interconnect between the network processor and traffic manager to other applications like the extensions to support Interlaken Look Aside as the interconnect for external memory interfaces. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.

The Open-Silicon Interlaken Protocol Controller IP supports the following Interlaken Alliance specifications:

• Interlaken Protocol Definition, v1.2

• Interlaken Look-Aside Protocol Definition, v1.1

• Interlaken Interop Recommendations, v1.4

Additional details regarding Open-Silicon’s Interlaken IP core can be found at http://www.open-silicon.com/capabilities/ip/interlaken-controller-ip.html.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, IP, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Open-Silicon’s High Speed Interconnect Protocol Ideal for “The Guaranteed Network”

MILPITAS, Calif. – December 6, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today ALAXALA Networks has integrated its Interlaken Controller IP into their next generation of high-performance network products. Taking advantage of the high-speed and scalability of the Interlaken interface, as well as Open-Silicon’s strong support team, ALAXALA was able to rapidly develop an ASIC that enables next-generation performance levels for their systems.

The Interlaken protocol is an integral part of today’s leading edge data networking products, enabling fast, scalable, and low-latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. This support for multiple industry-leading SerDes PHYs allows Open-Silicon’s customers to quickly integrate the core into their technology of choice.

“Since being introduced in 2006, Interlaken has grown significantly in its adoption and has proven to be a reliable solution for both high-bandwidth data streaming and look-aside interface applications. Networking devices which require zero down time and scalable performance can all benefit from the robust and flexible capabilities of the Open-Silicon Interlaken IP core,” said Jason Pecor, business development manager, Open-Silicon.

“ALAXALA is known for providing exceptionally reliable, high-performance routers and switches that operate at the heart of corporate networks and the networks of service providers and telecom carriers. Our use of this Interlaken Controller IP, along with Open-Silicon’s strong support team, helps ALAXALA drive network evolution and underscores our mission of providing ‘The Guaranteed Network,’” said Takashi Kumagai, department manager of LSI Design, ALAXALA Networks.

About the ASIC Interlaken IP Core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.

The Open-Silicon Interlaken Protocol Controller IP supports the following Interlaken Alliance specifications:

• Interlaken Protocol Definition, v1.2
• Interlaken Look-Aside Protocol Definition, v1.1
• Interlaken Interop Recommendations, v1.4

Additional details regarding Open-Silicon’s Interlaken IP core can be found at http://www.open-silicon.com/capabilities/ip/interlaken-controller-ip.html.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

ARM IP and Open-Silicon SoC Design Solutions leveraged for networking, telecommunications, storage and computing markets

MILPITAS, Calif. – October 24, 2011: Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, today announced the launch of its ARM® Center of Excellence. The new engineering group will focus on providing complete SoC development solutions for low-power chip development to the networking, telecommunications, storage and computing markets. To enhance the offering, Open-Silicon partnered with ARM through a comprehensive multi-year licensing agreement for the ARM® product portfolio.

The Open-Silicon ARM Center of Excellence offers complete SoC development solutions from chip architecture through to the shipment of fully packaged and tested silicon. A team of dedicated front-end design experts combined with leading technology including CoreMAX™ and low-power solutions like PowerMAX™ and VariMAX™ back biasing, allows customers to achieve market-differentiating performance and power levels in their ARM technology-based products. Open-Silicon can work with customers to rapidly develop their products from spec to production, taking advantage of the market need for energy efficient products. The complete services offering includes SoC architecture and analysis, AMBA-based RTL design, FPGA-based prototyping, transaction-level modeling, processor optimization hardening and custom embedded software development.

“The ARM Center of Excellence expands on Open-Silicon’s traditional strengths in networking and computing ASIC design by bringing in considerable depth of expertise in the embedded CPU space. This allows customers to focus on vertical-specific custom ASIC functionality or software applications while relying on Open-Silicon to quickly execute the rest of the SoC development at market-differentiating power and performance levels,” stated Hans Bouwmeester, director of Open-Silicon’s ARM Center of Excellence. “We see Cortex-A5 or A9 based home media gateways, for example, as one of the first networking areas to target with our combined capabilities and believe our ARM-based solutions will enable our customers to take full advantage of that market potential.”

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Partnership Combines ARM IP with Open-Silicon’s SoC Development Solutions

CAMBRIDGE, UK and MILPITAS, Calif. – 28 September, 2011: ARM and Open-Silicon, Inc. today announced that the companies have signed a comprehensive multi-year licensing agreement for a broad portfolio of ARM® technology. This includes ARM Cortex™ processors and associated ARM Processor Optimization Packs (POPs), ARM Mali™ Graphics Processing Units (GPUs) and ARM system IP. The latter includes ARM CoreLink™ interconnect and CoreSight™ debug and trace technology. The agreement enables Open Silicon to offer customers a ‘one-stop-shop’ where access to the latest ARM technology is complemented by the provision of SoC design, hardening, prototyping, software development and manufacturing services. Open-Silicon will use ARM technology to provide complete design and development services for low-power chip solutions focusing on the networking, telecommunications, storage and computing markets.

The combination of Open-Silicon’s SoC development capabilities and design experience with ARM technology will enable customers to benefit from a faster time to market and result in a more optimal solution. Open-Silicon’s architects can assist customers with architectural development using performance vs workload analysis, factoring in throughput and latency criteria to optimize peripheral IP selection. In addition, system security requirements for the protection of high-value data can be met through the careful application of ARM TrustZone® technology. Finally, Open-Silicon’s FPGA-based prototyping environments help software teams to engage early, accelerating system development and reducing program risk.

To optimize silicon implementation, Open-Silicon can access ARM Processor Optimization Packs (POPs) for Cortex processors, allowing customers to achieve leading performance implementations in a matter of weeks. Open-Silicon will further enhance customers’ results with its patented CoreMAX™ technology. When combined with Open-Silicon’s low-power solutions, including PowerMAX™ and VariMAX™ back biasing, CoreMAX allows customers to achieve market-differentiating performance and power efficiency.

“Having access to this broad portfolio of ARM IP will allow our systems architects to model various architectures and develop the best solutions for each customer. Open-Silicon’s goal is to provide solutions that enable our customers to get to market quickly with the best technology available,” said Dr. Naveed Sherwani, president and CEO of Open-Silicon. “As the demand for low-power products continues to drive the marketplace we believe our customers will benefit significantly from the combination of our first class design services and the latest ARM technology.”

As an ARM Partner, Open-Silicon is also part of the ARM Connected Community®, a global network of over 850 companies with access to a wide variety of resources and aligned to provide optimized solutions based on the ARM architecture.

“The strength of the ARM Partner ecosystem is based on rapid innovation, diversity and complimentary services. Open-Silicon’s experience in delivering ARM processor-based SoC solutions provides customers with a valuable service,” commented Lance Howarth, Executive Vice President of Marketing, ARM. “We are excited to work alongside Open-Silicon as they focus on a complete design service. The agreement paves the way for increased adoption of ARM architecture across a wide range of end markets, such as the use of Cortex-A5 processor in home gateway solutions.”

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

About ARM
ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:

 ARM is a registered trademark of ARM Limited. Cortex and MPCore are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM Inc.; ARM KK; ARM Korea Limited.; ARM Taiwan Limited; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium Services BVBA; ARM Germany GmbH; ARM Embedded Technologies Pvt. Ltd.; ARM Norway, AS and ARM Sweden AB

PowerMAX™ enables design for the lowest possible power

MILPITAS, Calif. – September 14, 2011: Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has issued U.S. Patent 7,941,776 related to Open-Silicon’s PowerMAX technology. Low power SoC design is a key differentiator for not just mobile applications, but also many networking, telecom, storage, and computing solutions. This new Open-Silicon patent focuses on lowering SoC dynamic and standby power by enriching the target standard library to best fit the needs of a particular design.

Specifically, this patent encompasses the intellectual property rights of Open-Silicon’s ZenCells™, standard cells created on-the-fly using PowerMAX’s design-specific library augmentation. ZenCells drive down both dynamic and leakage power through a method of closed-loop IC design optimization via the creation of design-specific cells from post-layout patterns. This optimization process involves automatically creating design-specific cells with desired characteristics, such as power, performance, or noise, which are then implemented as a standard cell from a set of post layout patterns. The pattern represents a part of or a whole standard cell and contains information regarding the pattern, such as layout, timing area, power and noise. Because these cells are created from post-layout patterns, the risks of prior dynamic library techniques are easily avoided. The result is cells that are optimized to satisfy the constraints imposed by the design context, thus bringing powerful design-specific customization to standard cell-based design methodology.

Introduced in 2008, PowerMAX is part of Open-Silicon’s Max Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer. Based on a strong foundation of conventional techniques, PowerMAX adds design-specific library augmentation, back biasing, power recovery and custom leakage signoff, resulting in the ASIC industry’s most complete low power design offering. The total Open-Silicon PowerMAX offering includes both the conventional techniques and the new technologies. By combining the best industry standard methods with novel technologies unique to Open-Silicon, customers can achieve the lowest power consumption possible for their silicon.

“Increasing levels of integration in performance-driven SoCs have challenged designers to come up with novel architectural and physical design solutions for power density limitations. At the other end of the spectrum, mobile applications are driving exponential growth in mobile performance, matched with every-increasing battery life requirements,” said Colin Baldwin, director of marketing for Open-Silicon. “Open-Silicon identified this growing problem early on and developed the MAX technologies to solve it. The award of this patent underscores Open-Silicon’s commitment to low power technology, and the company’s ability to provide its customers with better custom silicon.”

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Innovative Memory Solutions Focus on Data Networking and High-Performance Computing

MILPITAS, Calif. and BOISE, Idaho – June 7, 2011: Open-Silicon, Inc. and Micron Technology, Inc. (Nasdaq:MU) today announced that the companies have entered into an agreement that will enable them to explore opportunities around Micron’s recently announced Hybrid Memory Cube (HMC) products. The companies will initially focus on the data networking and high-performance computing markets. Open-Silicon’s depth of knowledge in these verticals and its broad ecosystem for ASIC, ASSP, and derivative IC development, combined with Micron’s cutting-edge HMC technology, offer a unique opportunity to create next-generation memory solutions optimized for various markets.

Micron’s HMC technology is a new architecture unique to the market today. It combines fast logic process technology with advanced DRAM, resulting in a memory system with revolutionary performance and power in a dramatically reduced footprint. As multi-core processing continues to advance semiconductor design to new levels, this technology provides memory and performance ideally suited to these next-generation systems.

“Open-Silicon offers the right mix of networking and computing architectural knowledge, semiconductor development expertise, and software and emulation services to support an expanding ecosystem developing around this new memory technology,” said Robert Feurle, Micron vice president of DRAM Marketing.

“Micron has developed groundbreaking memory technology that will enable a new level of system performance and integration, as well as new classes of applications that we are only beginning to understand today. We are proud to work with Micron on supporting Hybrid Memory Cube technology, and are excited to know that these solutions will be valuable to the data networking and computing markets that Open-Silicon presently serves,” said Naveed Sherwani, president and CEO of Open-Silicon.

About Micron
Micron Technology, Inc. is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets a full range of DRAM, NAND and NOR flash memory, as well as other innovative memory technologies, packaging solutions and semiconductor systems for use in leading-edge computing, consumer, networking, embedded and mobile products. Micron's common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

 ©2011 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. “Micron” and the Micron logo are registered trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This press release contains forward-looking statements regarding Hybrid Memory Cube. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents Micron files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically Micron's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for Micron on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.

Low-Power Device Showcases Advanced Technologies for Mobile Applications

MILPITAS, Calif. – June 7, 2011: Open-Silicon, Inc. announced today it achieved a key milestone in demonstrating its low-power design capability on GLOBALFOUNDRIES’ 28nm super low-power (SLP) technology. Utilizing Open-Silicon’s PowerMAX™ and VariMAX™ low-power design technologies, Open-Silicon successfully taped out an ultra-low power ASIC on GLOBALFOUNDRIES’ 28nm-SLP technology. In the device, variation and leakage are controlled through the combination of Open-Silicon’s body biasing technology and GLOBALFOUNDRIES’ high-k metal gate (HKMG) process. The low-power, high-gate-density chip is ideal for mobile applications such as smart phones, where power conservation is necessary for battery life and where high-speed processors are critical to the user’s application experience.

Designed and developed using Open-Silicon’s 28nm methodology, the new ASIC benefits from Open-Silicon’s MAX Technologies™ including VariMAX for body biasing to manage silicon process variation and provide leakage control. Biasing technologies are common in the standard product space for mobile devices due to their power reduction and process yield benefits, yet rarely offered in the ASIC space. Open-Silicon’s VariMAX technology addresses this industry shortfall by offering state-of-the-art biasing control combined with open-market standard cell libraries and a GLOBALFOUNDRIES reference flow.

Open-Silicon joined GLOBALFOUNDRIES partner ecosystem, GLOBALSOLUTIONS, when it was launched in June 2010. The open and collaborative ecosystem leverages the best resources from around the world to deliver optimized solutions. The GLOBALSOLUTIONS ecosystem partners are evaluated and certified to meet specific service and quality criteria, helping to reduce risk and increase the probability of first-time-right designs.

GLOBALFOUNDRIES’ 28nm-SLP targets low-power applications including cellular base band, application processors, portable consumer and wireless connectivity devices. 28nm-SLP utilizes HKMG and presents the same dense routing of 28nm HP, but is a lower cost technology in terms of the performance elements utilized to boost carrier mobilities. The 28nm-SLP transistors offer up to 40 percent increased speed at the same leakage relative to 40nm-LP with a 40 percent reduction in energy/switch (at nominal operating voltages of 1.0V for 28nm-SLP and 1.1V for 40nm-LP, and up to a 50 percent speed increase and power savings with overdrive: 1.1V for 28nm-SLP and 1.2V for 40nm-LP).

“As geometries continue to decrease, technologies like VariMAX and PowerMAX increase in value by providing additional power reduction or variation management that otherwise would be unobtainable. Body biasing, in particular, was found to be extremely effective when combined with HKMG technology to manage standby-mode leakage. Proving this low-power technology in GLOBALFOUNDRIES’ 28nm process gives ASIC customers the same state-of-the-art process technology and leakage-reduction methodologies that IC standard product vendors benefit from in mobile products,” said Taher Madraswala, vice president of engineering, Open-Silicon, Inc.

“With red-hot demand and steep competition in the mobile market, designers face increased challenges as they balance the need for increased functionality with a shrinking power budget, while delivering products on time in tight market windows. For those customers looking for a proven design services partner to aid them in this process, GLOBALFOUNDRIES is pleased to support Open-Silicon, a key partner in our GLOBALSOLUTIONS ecosystem, in its low-power initiative and to enable its ability to demonstrate solutions in silicon on GLOBALFOUNDRIES’ 28nm-SLP technology,” said Srinivas Nori, director of ASIC solutions at GLOBALFOUNDRIES.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

New Program Raises the Industry Bar on Schedule Predictability

MILPITAS, Calif. – May 27, 2011: Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, today introduced the semiconductor industry’s first money-backed design engineering schedules. Open-Silicon will meet the schedule, delivering a prototype on time, or the company will refund the cost of the design engineering, up to $500K.

In order to meet time-to-market goals and realize an integrated circuit’s (IC) true market potential, execution to schedule is paramount. The semiconductor industry, however, does not have a good track record of delivering products on time, resulting in missed revenue. Open-Silicon has focused on meeting schedules since its first chip and continues to be held accountable at every board of directors’ meeting. While the company has always considered schedule predictability extremely important, the company is now willing to sign up on qualifying programs that the engineering will be “On Time, or On Us.”

“The semiconductor industry needs schedule predictability to be viewed with the same intense focus as design functionality. Open-Silicon’s bold statement with “On Time, or On Us” is a call to customers and partners to address schedule predictability as the key concern for the coming decade,” said Dr. Naveed Sherwani, CEO of Open-Silicon. “We founded Open-Silicon on this principle, and are now again taking a leadership position by putting our money behind it.”

“On Time, or On Us” Offer Details
The “On Time, or On Us” offer is valid on qualifying designs in 40nm or 65nm process, where design schedules are still relatively long and where Open-Silicon has a well-matured design methodology. Under the terms of this program, the originally quoted design non-recurring engineering (DNRE) charge will be refunded, up to $500K, for programs that miss the committed development schedule for prototype delivery. This program will run through December 2011. To learn more about the program, visit http://www.open-silicon.com/capabilities/program-management/on-time-or-on-us.html.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Interlaken IP Achieves Key ASIC Market Milestone

MILPITAS, Calif. – May 24, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today it has received its 20th ASIC license for the Open-Silicon Interlaken IP core. In addition, the IP has been taped out in 28nm technology and is now silicon proven at 40nm.

“This achievement comes on the heels of a recent competitive Interlaken IP provider acquisition by an FPGA company. We want to highlight the capability of our Interlaken IP, as well as reassure our current and future ASIC customers that we will continue to provide a high quality core and product support,” said Jason Pecor, senior product manager at Open-Silicon. “Open-Silicon is presently in development of the next generation IP core in our Interlaken roadmap.”

In March 2011, Open-Silicon announced recent updates to the Interlaken IP core, including fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical and physical SerDes lanes provides the flexibility necessary to ease board-level design complexities for very high-speed chip-to-chip serial interfaces.

About the ASIC Interlaken IP Core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.

The Interlaken protocol is an integral part of today’s leading edge data networking products, enabling fast, low latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. This support for multiple industry-leading SerDes PHYs allows Open-Silicon’s customers to quickly integrate the core into their technology of choice.

Additional details regarding Open-Silicon’s Interlaken IP can be found at http://www.open-silicon.com/capabilities/ip.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Additional configurability and flexibility facilitates complex board-level designs for data networking, storage and high-performance computing customers

MILPITAS, Calif. – March 10, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today the availability of an enhanced version of its Interlaken controller IP core. The updated core features fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical and physical SerDes lanes provides the flexibility necessary to ease board-level design complexities for very high-speed chip-to-chip serial interfaces.

This latest feature is an evolution of the silicon-proven Open-Silicon Interlaken HiFlex architecture, which has been successfully deployed in multiple ASIC technologies addressing applications from 40Gbps to 300Gbps. The new version also carries forward existing HiFlex features such as Interlaken-LA, In-Band and Out-of-Band flow control, multiple user-interface options, flexible statistics counters and built-in interrupt structures. This controller is fully compliant with the latest Interlaken Protocol Definition (v1.2), the Interlaken Look-Aside Protocol Definition (v1.1), and the Interlaken Interop Recommendations (v1.4).

About the ASIC Interlaken IP Core
Combining the advantages of popular SPI4.2 and XAUI interfaces, the Interlaken protocol builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology. Open-Silicon’s Interlaken IP can scale from 10Gbps to over 300Gbps of bandwidth through the combination of SerDes speed (3.125Gbps to 12.5Gbps) and a variable number of SerDes lanes (1 to 24). This scalability makes Interlaken ideal for multiple generations of future network switches, routers and storage equipment.

The Interlaken protocol is an integral part of today’s leading edge data networking products, enabling fast, low latency chip-to-chip communication for switching, routing, and deep packet processing applications. Architected to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. This support for multiple industry-leading SerDes PHYs allows Open-Silicon’s customers to quickly integrate the core into their technology of choice.

“Open-Silicon is focused on providing solutions to help customers get their networking, storage, and computing SoCs to market quickly,” said Naveed Sherwani, CEO and president for Open-Silicon. “From architecture services to software development to this latest generation of our industry-leading Interlaken IP core, Open-Silicon provides comprehensive, flexible solutions for various development models including traditional ASIC design and newer derivative SoC design engagements.”

Additional details regarding Open-Silicon’s Interlaken IP can be found at http://www.open-silicon.com/capabilities/ip.

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

MILPITAS, Calif. – February 15, 2011: Open-Silicon, Inc., a leading semiconductor design and manufacturing company, today announced the availability of MAX Technologies 2.0. This update to Open-Silicon’s MAX Technologies helps Open-Silicon best optimize silicon for power, performance and cost while also managing the process variability of today’s advanced CMOS nodes. Not only are power, performance, cost and variability major design challenges for 40nm and 28nm SoCs, but they also are the criteria by which great silicon is measured in the market. By using PowerMAX™, CoreMAX™, TestMAX™ and VariMAX™, Open-Silicon’s customers can enjoy competitive advantages in their marketplace.

For managing silicon variability and reducing leakage power, Open-Silicon offers VariMAX with back biasing. Open-Silicon’s 28nm development efforts have shown back biasing to be effective at dramatically reducing leakage power even with new high-K metal gate (HKMG) transistors. As low-power design moves to the mainstream, back biasing is becoming a critical technology for maximizing yields for high-volume mobile SoCs and managing power density for high-performance networking and computing silicon.

Open-Silicon offers PowerMAX for low-power design. In particular, Multi-Threshold CMOS (MTCMOS) has been used in many designs across multiple foundries. With MTCMOS, Open-Silicon has efficiently implemented block-level power gating using either header or footer cells as well as memory retention, state retention flops, level shifters, isolation cells and rush current analysis.

For high performance, Open-Silicon offers 28nm support for design-specific library augmentation, where Open-Silicon uses patented software to analyze the critical paths and design new library cells to improve performance. Think Physical™, another addition to the MAX Technologies line, helps designers create physically-optimized RTL by carefully and simultaneously modeling the design’s physical considerations. By outlining the entire design flow, from architecture all the way through to tape-out, before any code is written, team members can understand how the specific constraints of the architecture, technology, verification environment, synthesis flow and place and route flow mutually interact. This careful attention throughout the design process means overall design performance is maximized.

“As the industry moves toward a design-lite model, Open-Silicon is uniquely positioned to provide the derivative solutions our customers need,” said Colin Baldwin, director of marketing at Open-Silicon. “MAX Technologies 2.0 further enhances our capabilities to design and manufacture complex, custom silicon solutions, and builds our customer’s confidence that they are going to be supplying world-class silicon to these new derivative markets.”

About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

BANGALORE, INDIA, Nov 15, 2010 -- Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc,, announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence(R) Silicon Realization product line. Open-Silicon completed the entire design using Cadence's integrated end-to-end Encounter(R) digital design, implementation, and manufacturability signoff technology.

"Cadence offers a complete suite of tools for designing ASICs and strong customer support. We have fine tuned the tools and found good results from synthesis through to tapeout. Cadence's Silicon Realization technology has also been a key contributor to our ongoing efforts to increase our predictability and reliability, both of which are critical to the Open-Silicon custom silicon solution," said Taher Madraswala, vice-president of engineering at Open-Silicon.

Open-Silicon's chips go into products where performance, power and time-to-market are paramount. Cadence's Silicon Realization product line optimizes logical, physical, electrical, and manufacturing effects concurrently, eliminating iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start, thereby achieving the objectives of performance, power, and cost.

"We see Cadence as a key collaborator for Open-Silicon as we move towards 28-nanometer design and as the industry moves towards a design-lite model," said Dr. Naveed Sherwani, president and CEO of Open-Silicon, Inc. "We are confident that working with Cadence will help us achieve our customers' specific goals."

Cadence recently announced a new holistic approach to Silicon Realization that moves chip development beyond its traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. The new approach is focused on offering products and technologies that deliver on the three essential requirements for a deterministic path to silicon: unified design intent, abstraction and convergence. A key element of the Cadence EDA360 strategy, this approach is aimed at boosting productivity, predictability and profitability while reducing risk.

"The 2.4 GHz processor that Open-Silicon has taped out is a testament to the company's expertise in designing cutting-edge, high-performance chips," said Chi-Ping Hsu, senior vice president of R&D, Silicon Realization Group at Cadence. "We are excited that our high-performance Silicon Realization product line has enabled Open-Silicon to demonstrate ultra high levels of ASIC processor performance while also helping improve their time-to-market performance."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Open-Silicon Strengthens Patent Portfolio with Test Technology

TestMAX’s Scan-Frequency Scaling technology reduces test time and device cost

MILPITAS, Calif. – November 9, 2010: Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has issued U.S. Patent 7,805,648 related to Open-Silicon’s TestMAX technology. As a part of Open-Silicon’s custom silicon solution, scan-frequency scaling reduces silicon test time providing customers with an additional way to decrease overall device cost.

Introduced in 2009, TestMAX is part of Open-Silicon’s MAX Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer. As design gate counts continue to grow exponentially, both wafer probe and final test costs increase. TestMAX addresses this challenge by significantly reducing test time, and therefore lowering device cost. Other significant benefits are that it requires no design changes, is scan-architecture independent, and can be applied on previously taped out designs.

Scan-Frequency Scaling
Traditional scan testing frequencies are limited by the power dissipation in the device under test. By first profiling the scan vectors for power dissipation, Open-Silicon is able to select those tests with lower thermal impact and power mesh currents and greatly increase their frequency.

“The granting of this patent underscores the strength and execution of Open-Silicon’s technology solutions,” said Colin Baldwin, Director of Marketing at Open-Silicon. “Fully custom silicon that wins in the market requires a lot more than today’s readily-available EDA tools. Our team of experienced engineers is focused on solutions that enable the creation of custom silicon that touts optimal power and performance, while reducing cost and accelerating time-to-market.”

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenMODEL brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Open-Silicon Expands Presence in India With New SoC and Systems Solution Center

Additional Global Facility Meets Increasing Demand for Derivative SoC Solutions

BANGALORE, India – November 1, 2010: Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, announced today that it has opened an office in Pune, India to meet the increasing demand for derivative SoCs and platform solutions. The Pune facility is the second for Open-Silicon in India; the Open-Silicon Bangalore facility is now in its seventh year of successful operations. The new Pune engineering center will focus on system architecture, RTL design and design verification as well as take a leading role in providing emulation, validation and embedded software solutions for SoC platform customers.

The new engineering center in India comes on the heels of the October opening of a system design center in the Research Triangle Park area in Raleigh, North Carolina. As Open-Silicon increases its front-end design capabilities worldwide, the company strengthens its capability to provide complete solutions ranging from physical design and manufacturing to complex architecture and RTL design. Furthermore, Open-Silicon’s business model is significantly different from the traditional time & materials models of many design service companies, making Open-Silicon the only true end-to-end solutions provider in the ASIC/SoC market.

As the semiconductor industry shifts from fab-lite towards a design-lite model, Open-Silicon is uniquely poised to collaborate with customers’ engineering teams. This engineering collaboration allows customers to add revenue to an existing IC product line, without pulling their core design engineering team from the next generation core product roadmap focus. The net result is a greater return on the overall product line investment.

“Our expansion in India underscores our commitment to derivative SoCs and platform solutions,” said Shrikrishna Gokhale, Open-Silicon’s chief operating officer and managing director India. “There is a large pool of talent in Pune with strong IC product development and embedded software skills. Our ability to offer complete turnkey and derivative product development, including embedded software, allows Open-Silicon to offer comprehensive semiconductor product development solutions to our customers looking for collaboration partners.”

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenMODEL brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com.

New Collaborative Engineering Center in Research Triangle Park Opens to Meet Increasing Demand

MILPITAS, Calif. – October 27, 2010: Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, announced today that it has opened an office in the Research Triangle Park (RTP), centrally located between Raleigh, Chapel Hill and Durham, North Carolina, to meet the increasing demand for derivative SoC solutions. The new engineering center will focus on ASIC architecture, RTL design and design verification as a part of the company’s existing derivatives design offering first launched several years ago with the development of an NXP chip in a record-breaking timeframe. Located near cutting edge universities and several large technology companies, the new development center provides Open-Silicon with an additional global facility to support its growing customer base with experienced system design engineers.

As a collaborative engineering partner, Open-Silicon offers the complex architecture, RTL design and design verification solutions required to enable turnkey and derivative SoC development. This allows customers to add revenue to an existing IC product line through modifications to that design without pulling the engineering team from its next generation core product roadmap focus. The net result is a greater return on the overall product line investment.

With the previously announced 2009 acquisition of Silicon Logic Engineering (SLE), Open-Silicon grew the company’s solutions offering from physical design and manufacturing to include the complex architecture and RTL design required to build complex SoCs in vertical markets such as networking, telecom, storage and computing. The company’s expanded in-house engineering teams work with Open-Silicon’s existing design partners to meet the specific needs of each customer and design.

“Last year, when SLE joined Open-Silicon, we knew we had found a great front-end design team to compliment our comprehensive physical design team and design partners. Our customer response has been extremely positive to the integration of the derivatives design capabilities into our solutions offering,” said Scott Houghton, vice president marketing and business development at Open-Silicon. “Adding this new facility for front end design, in a location with ready access to top tier talent, will help us continue to meet our customers’ needs.”

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenMODEL brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

Open-Silicon to Discuss The Future Platforms of Computing At CASPA Annual Conference

MILPITAS, Calif. – October 20, 2010 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that its CEO, Dr. Naveed Sherwani, will participate in a panel at the Chinese American Semiconductor Professional Association (CASPA) 2010 Annual Conference. Dr. Sherwani, along with two other industry leaders, will discuss the “Future Platforms of Computing.” The theme of Dr. Sherwani’s presentation is “Moving Toward Design-Lite for Innovation.”

What: CASPA Panel, “Future Platforms of Computing”

When: Saturday, October 23, 2010, 1:45 p.m. - 5:15 p.m. PDT

Where: Santa Clara Convention Center, Santa Clara, CA

Who:
Moderator: Liang Peng, CASPA BoD; Platform Architect, Intel

Panelists: Kamwar Chadha, Chief Marketing Officer, CSR; Co-founder of Sirf

Bryon Shaw, Managing Director of Advanced Technology, General Motors

Dr. Naveed Sherwani, Co-Founder, President & Chief Executive Officer, Open-Silicon, Inc.

Abstract: The discussion, “Moving Toward Design-Lite for Innovation” will address planning for the future of not only the electronics industry, but the entire global economy, including strategies for reducing our carbon footprint. Companies must take a holistic approach and consider their impact across the entire product life cycle. There are many points across a design, from architecture level to production level, where optimization for low power can happen. Meanwhile, the industry is moving toward optical interfaces to enable higher bandwidth. While innovation requirements coexist with time-to-market pressures, companies are seeking new ways to maximize the return on their product investments. One of these strategies includes Design-lite. Design-lite enables a company’s engineering team to focus on the core product roadmap, while utilizing the design capabilities of another company, like Open-Silicon, to build derivatives of those products.

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenMODEL brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

MILPITAS, Calif. – October 7, 2010: Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that its CEO, Dr. Naveed Sherwani, will participate in a panel at the Semiconductor Manufacturing International Corporation (SMIC) 2010 Technology Symposium. Dr. Sherwani, along with five other industry leaders, will discuss the IP/SOC ecosystem for today’s complex designs and advanced technology. The theme of the symposium is “Partnership for Success.” What: SMIC Panel, “IP/SOC Ecosystem for Today’s Complex Designs and Advanced Technology”

When: Friday, October 8, 2010, 1:30 p.m. - 2:30 p.m. PST

Where: Santa Clara Convention Center, Santa Clara, CA

Who:
Moderator:
Wen Huang, Vice President, Corporate Marketing, SMIC

Panelists:
Mahesh Tirupattur, Executive Vice President, Analog Bits
Dr. Dipesh Patel, Vice President, Engineering, ARM
Brian Gardner, Group Director, Cadence
Dr. Naveed Sherwani, Co-Founder, President & Chief Executive Officer, Open-Silicon, Inc.
Navraj Nandra, Senior Director, Marketing, Synopsys
Dr. Wayne Dai, Chairman & CEO, VeriSilicon

Panel Abstract:
The panel, “IP/SOC Ecosystems for Today’s Complex Designs and Advanced Technology,” will address licensed IP from IP vendors versus design service parties, and the pros and cons for each model; IP interoperability versus migration and how customers can benefit from the interoperability between foundries during the migration from current technology to advanced technology; the tradeoff in IP platforms versus subsystems and the choices customers are faced with; the IP forecast down the road and the role of EDA, design services and foundries, as well as the hurdles for advanced technologies; and IP identification and protection and the standards and implementations associated with these.

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenModel brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.

MILPITAS, SUNNYVALE and SAN JOSE, Calif. – September 21, 2010: Open-Silicon, Inc. , MIPS Technologies, Inc.(NASDAQ: MIPS), and Dolphin Technology today announced the successful tapeout of a high-performance ASIC processor at over 2.4GHz under typical conditions.  This achievement, as measured in timing closure against TSMC reference flow signoff conditions, will make this one of the highest frequency ASIC processors ever built, highlighting the companies’ industry-leading technologies for building high-performance processor-based systems.  This high-performance ASIC processor is a follow-on test chip to the 65nm, 1.1GHz test chip announced by Open-Silicon and MIPS Technologies at the end of last year.

The device contains a MIPS32® 74Kf™ processor core, a superscalar, out-of-order (OoO) CPU with high-performance integrated Floating-Point-Unit (FPU), DSP Extensions, 32K L1 Instruction & 32K L1 Data Cache memories and on-chip 8K PDtrace™ memory buffer.  The MIPS32 74K® core is a fully synthesizable, licensable IP core with a 15-stage pipeline for achieving maximum frequencies, and is widely used in high-end digital consumer devices, set-top boxes, and home networking solutions. As with the prior 65nm generation design, RTL design was done by MIPS Technologies, and implementation using the Dolphin memories was done by Open-Silicon.  TSMC is fabricating the device using its CyberShuttle™ prototyping program. 

To maximize the performance, Open-Silicon utilized its CoreMAX(tm) technology for design-specific library augmentation.  For this design, 159 new LVt cells, 147 RVt, and 147 HVt cells were created by Open-Silicon to specifically optimize the critical paths inside the MIPS 74Kf core and FPU.  Other advanced physical design techniques included Open-Silicon’s experienced processor floorplanning, clock tree synthesis using useful skew, and timing-driven placement optimization. Cadence® EDA layout tools were used for physical design.

“The collaboration between Open-Silicon, MIPS Technologies and Dolphin Technology to develop one of the fastest ASIC processors ever built has proven our combined design capabilities and the strength of the model,” said Dr. Naveed Sherwani, CEO and president of Open-Silicon.  “Processor performance optimization is a key requirement for next generation derivative SoCs and ASICs.  We continue to invest in our processor design capabilities, including the MAX Technologies, to provide customers with the best possible custom silicon.”

“Our 74K cores, which are widely licensed for applications in the digital home, broadband, and wireless networking markets, provide the only licensable CPU IP cores with a 15-stage pipeline, and offer the highest single-core performance in our current portfolio,” said Sandeep Vij, CEO and president of MIPS Technologies. “The 74K core was an ideal candidate to demonstrate top-end performance on a 40nm test chip. We’re pleased that we were able to achieve over 2.4 GHz in our joint effort with Open-Silicon and Dolphin, and believe this achievement compares favorably with frequency results seen on other IP in 40nm, and even 28nm processes.”

“Dolphin Technology, a leading provider of Silicon IP for over 16 years, continually strives to help our partners and customers surpass their design targets,” said Mo Tamjidi, CEO, Dolphin Technology. “Achieving breakthrough performance at over 2.4 GHz in 40nm demonstrates the extensive experience of the teams at Dolphin, MIPS and Open-Silicon.”

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenModel <http://open-silicon.com/asic-design/openmodel>  brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award <http://www.gsaglobal.org/awardsdinner/2009/awards.asp>  for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com <http://www.open-silicon.com/>  or call 408-240-5700.

About MIPS Technologies, Inc.
MIPS Technologies, Inc. (NASDAQ: MIPS) is a leading provider of industry-standard processor architectures and cores that power some of the world's most popular products for the home entertainment, communications, networking and portable multimedia markets. These include broadband devices from Linksys, DTVs and digital consumer devices from Sony, DVD recordable devices from Pioneer, digital set-top boxes from Motorola, network routers from Cisco, 32-bit microcontrollers from Microchip Technology and laser printers from Hewlett-Packard. Founded in 1998, MIPS Technologies is headquartered in Sunnyvale, California, with offices worldwide. For more information, contact (408) 530-5000 or visit www.mips.com <http://www.mips.com/> .

About Dolphin Technology, Inc.
Dolphin Technology, Inc., is a leading provider of high performance Semiconductor Intellectual Property (SIP) blocks that include embedded memory and memory compiler products, high performance and standard IOs and high performance standard cell libraries.
Advanced design technology incorporated into Dolphin's SIP blocks enable SoC (System on Chip) designs to achieve faster clock rates, smaller die size and reduced manufacturing cost. For more information about Dolphin and its products, please visit (www.dolphin-ic.com <http://www.dolphin-ic.com/> ).


CoreMAX is a trademark of Open-Silicon, Inc. MIPS, MIPS32 and 74K are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc.  All other trademarks referred to herein are the property of their respective owners.

 
High-Quality, Fully Verified IP and Longstanding Relationship Between the Two Companies Accelerates Time-to-Market for Open-Silicon’s Customers

MOUNTAIN VIEW, Calif. – July 7, 2010 — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Open-Silicon , a leading system-on-chip (SoC) design and semiconductor manufacturing company, has licensed and integrated 50 high-speed DesignWare® IP products into customers’ chips with 100 percent first-pass silicon success. The IP products include complete solutions consisting of configurable digital controllers, PHYs which support leading process technologies from 180 to 28 nanometers, verification IP, as well as analog front ends and data converters. In addition to integrating many of Synopsys’ silicon-proven interface and analog IP products, Open-Silicon has incorporated building block and infrastructure IP from Synopsys’ DesignWare Library into hundreds of designs. By accessing a broad range of pre-verified IP solutions from a trusted vendor, Open-Silicon has been able to consistently reduce integration and verification risk and shorten development cycles for their complex designs in a wide range of applications such as home networking, enterprise network processors, wireless base-stations, storage controllers and test equipment.

“Our customers look to us to execute complex interfaces with first time silicon success, including physical design, package design, and test engineering,” said Taher Madraswala, Vice President of Engineering at Open-Silicon.  “Our 100 percent success rate when using DesignWare IP is a reflection of Open-Silicon’s IP integration capability, our tight technical relationship with Synopsys’ engineers, and the high quality of Synopsys’ complete solutions of silicon-proven DesignWare IP.”

As one of the initial members of the Synopsys IP OEM Partner Program, Open-Silicon has access to the entire Synopsys portfolio of interface and analog IP solutions. As companies increasingly turn to leading SoC design and semiconductor manufacturing vendors like Open-Silicon to help build their complex SoC designs, Synopsys is proactively partnering with these vendors to provide silicon-proven IP solutions, expert technical support and comprehensive documentation to mitigate project risks. Synopsys and Open-Silicon provide customers with high-quality IP and design services that help them bring their products to market faster and with more differentiated features.

“For more than 15 years, Synopsys has been providing SoC designers with a broad portfolio of high-quality, silicon-proven IP solutions consisting of digital controllers, PHYs and VIP that reduce integration risk and development cost and speed time-to-market for SoC designs,” said John Koeter, Vice President of Marketing for the Solutions Group at Synopsys. “As one of the industry’s top fabless ASIC companies, Open-Silicon is focused on customer service, low cost, design schedules and first-time correct silicon. Our OEM partnership with Open-Silicon enables a larger customer base to access pre-qualified DesignWare IP allowing them to reduce development costs and risk.”

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven interface and analog IP solutions for system-on-chip designs. Synopsys’ broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analog IP family includes Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC™ transaction-level models to build virtual platforms for rapid, pre-silicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware <http://www.synopsys.com/designware> . Follow us on Twitter at http://twitter.com/designware_ip. 

 
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/ <http://www.synopsys.com/> .

About Open-Silicon, Inc.
Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenModel <http://open-silicon.com/asic-design/openmodel> brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award <http://www.gsaglobal.org/awardsdinner/2009/awards.asp>  for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com <http://www.open-silicon.com>  or call 408-240-5700.

# # #
Synopsys and DesignWare are registered trademarks of Synopsys, Inc.  SystemC is a trademark of the Open SystemC Initiative and is used under license. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

MILPITAS, Calif. – June 22, 2010: Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, today announced the promotion of Taher Madraswala to Vice President of Engineering. He will continue driving the on-time execution of customers’ SoC and ASIC design and development programs.

Madraswala joined Open-Silicon at its inception in 2003 and served as director of ASIC Program Management where he was instrumental in building the company’s business model, OpenMODEL™, and particularly Open-Silicon’s unique model for ASIC Program Management. His career accomplishments include more than 22 years of semiconductor engineering experience – twelve of which were devoted to designing microprocessors for Intel Corp. To date, Taher Madraswala has the distinction of being part of more than 150 tapeouts throughout his career. His focus has been on taking an architecture spec to gds2 and he has extensive experience in micro-architecture design, custom circuit design, RTL and physical design, and test among other parts of the design process.

As VP of Engineering, Madraswala will report to Shrikrishna Gokhale, Chief Operating Officer and Managing Director-India. He will be responsible for the development of strategic planning, managing the design engineering teams, and for overseeing the implementation of Open-Silicon’s proven design methodologies.

“Taher’s expertise in handling complex designs and managing Open-Silicon’s design methodology has been key to our success in providing customers with consistent delivery of reliable silicon,” said Dr. Sherwani. “His extensive experience in hands-on design and his leadership skills will be an asset in leading our design engineering teams today and as we move forward.”

Madraswala earned a Master’s degree in Computer Engineering for the University of Louisiana, Lafayette, and an undergraduate degree in Electrical Engineering from Aligarh University.

About Open-Silicon, Inc.

Open-Silicon, Inc. is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. Open-Silicon’s OpenModel brings together Open-Silicon’s engineering technology and high-quality manufacturing services with one of the broadest partner ecosystems for IC development, spanning IC design, open market IP integration, wafer fabrication, and assembly/test services. Open-Silicon received the Global Semiconductor Alliance (GSA) award for Most Respected Private Semiconductor Company in 2008 and 2009. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.