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Open-Silicon to Showcase Spec2Chip IoT SoC Platform and Comprehensive HBM2 IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+ at 2017 TSMC Europe OIP Ecosystem Forum and Technology Symposium, Amsterdam…

Open-Silicon, a system-optimized ASIC solutions provider, will be exhibiting at the 2017 TSMC Europe OIP Ecosystem Forum and Technology Symposium, Amsterdam to demonstrate the company’s IoT Edge SoC Platform and IoT Gateway SoC Platform. Please visit our booth on the exhibition floor to view the demos and to learn about other innovative ASIC/SoC solutions, including the comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+.

  1. IoT Edge SoC Platform This demonstrates end-to-end communication between sensor hubs and the cloud through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. The industrial IoT system setup is a part of Open-Silicon’s Spec2Chip IoT SoC Platform, which allows IoT edge ASIC designs to be evaluated at the system level. http://www.open-silicon.com/iot-edge-soc-platform/
  1. IoT Gateway SoC Platform – This demonstrates end-to-end communication between edge devices/sensor hubs, gateways and the cloud. The IoT Gateway SoC Platform applications include smart homes, smart waste management, smart transport, smart traffic, smart parking, smart lighting, smart metering and more. Open-Silicon’s booth demonstration will include smart lighting and smart parking in action. This smart city IoT system setup is a part of Open-Silicon’s Spec2Chip IoT SoC Platform, which allows IoT gateway ASIC designs to be evaluated at the system level. http://www.open-silicon.com/iot-gateway-soc-platform/

Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+:
This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon’s IP fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D Interposer.

When and Where:
Open-Silicon booth on exhibition floor
Open Innovation Platform® Ecosystem Forum, June 12, 2017
Technology Symposium, June 13, 2017
Hilton Amsterdam Airport Schiphol
Schiphol Boulevard 701
Amsterdam, 1118BN Netherlands

About Open-Silicon:
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system, software, IP – and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies, ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.

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Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions.  All other trademarks are the property of their respective holders.