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Open-Silicon to Exhibit at TSMC Technology Symposium, Santa Clara, Wednesday, March 15, 2017…

Open-Silicon, a system optimized ASIC solutions provider, will be exhibiting at the TSMC Technology Symposium 2017, Santa Clara to demonstrate the company’s IoT ASIC Platform. Visit our booth to learn about 28Gbps SerDes Evaluation Platform, HMC 2.0 Memory Controller ASIC IP and Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+.

  1. IoT ASIC Platform – This demonstrates end-to-end communication between sensor hubs and cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. The Industrial IoT system setup is a part of Open-Silicon’s Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at system level.
  2. 28G SerDes Evaluation Platform – This evaluation platform for ASIC development will enable the rapid deployment of chips and systems for high bandwidth networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
  3. HMC 2.0 Memory Controller ASIC IP – This IP demo will showcase a platform based on Xilinx Virtex-7 XC7VX690T FPGA that includes a fully validated design that integrates HMC controller along with HMC exerciser functions. The demo platform allows quick evaluation of the HMC technology and performance testing of the HMC links.

Solutions:
Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+. The solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon’s IP fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die IO needed to drive the interface between the logic-die and the memory die-stack on the 2.5D Interposer.

WHEN: Wednesday, March 15th 2017,
Time: 8:30a.m. – 5:30p.m.

WHERE: Booth 919 on exhibit floor, in Zone: VCA/DCA,
Santa Clara Convention Center,
5001 Great America Pkwy,
Santa Clara, CA 95054.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system, software and IP – and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date.  Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.  www.open-silicon.com

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Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions.  All other trademarks are the property of their respective holders.