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Open-Silicon to Exhibit at GSA Entrepreneurship Conference, Belgium to demonstrate its IoT Edge SoC Platform Solution, IoT Gateway SoC Reference Design and Comprehensive HBM2 IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+…

Open-Silicon, a system-optimized ASIC solutions provider, will be exhibiting at GSA Entrepreneurship Conference, Leuven, Belgium on September 27, 2017. The company will demonstrate its IoT Edge SoC Platform Solution, IoT Gateway SoC Reference Design and Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+.

  • ARM® Cortex®-M based IoT Edge SoC Platform Demonstration –This demonstration shows the end-to-end communication between sensor hubs and the cloud through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. The industrial IoT system setup is a part of Open-Silicon’s Spec2Chip IoT SoC Platform, which allows IoT edge custom SoC designs to be evaluated at the system level.
  • ARM® Cortex®-A9 based IoT Gateway SoC Reference Design Demonstration–This demonstration shows the IoT Gateway SoC Reference Design, which is built for smart city applications such as smart homes, smart waste management, smart transport, smart traffic, smart parking, smart lighting, smart metering and more. The gateway is a full featured device that supports various types of wireless and wireline connectivity, communicates with IoT edge devices and connects to the cloud through 3G/LTE/WiFi. Open-Silicon’s smart city IoT system setup is a part of Open-Silicon’s Spec2Chip IoT SoC Platform, which allows IoT gateway custom SoC designs to be evaluated at the system level.
  • Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+ – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon’s IP fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer.  http://www.open-silicon.com/high-bandwidth-memory-ip

When: September 27, 2017
Where:  On the Exhibition Floor, GSA Entrepreneurship Conference, Leuven, Belgium.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.  To learn more, visit www.open-silicon.com

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.