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Open-Silicon to Exhibit, participate in a panel and deliver two Tech Talks at IP SoC 2017, Bangalore on Wednesday, April 5, 2017…

Open-Silicon, a system optimized ASIC solutions provider, will be participating at the D&R IP SoC 2017, Bangalore. Company will make two technical presentations on “Role of 3rd Party IP Selection and Integration in ASICs” and “Interlaken – High Speed Chip-to-Chip Interface IP supporting 1.2Tbps bandwidth and up to 56Gbps SerDes”. Besides tech talks company will also be demonstrating it’s IoT Gateway SoC Platform, IoT ASIC Platform and present various IP solutions including Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+, HMC 2.0 Memory Controller ASIC IP and Interlaken IP. Open-Silicon will also participate in a panel titled, “IP Value on Programmable Devices or Embedded Programmable Blocks: Future and Vision”.

Exhibits:
IoT Gateway SoC Platform  – Company will be demonstrating end-to-end communication between edge devices / sensor hubs, gateway and cloud. The IoT Gateway SoC Platform applications include Smart Homes, Smart Waste Management, Smart Transport, Smart Traffic, Smart Parking, Smart Lighting, Smart Metering, etc. At its booth, company will be demonstrating Smart Lighting and Smart Parking in action.

IoT ASIC Platform This demonstrates end-to-end communication between sensor hubs and cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. The Industrial IoT system setup is a part of Open-Silicon’s Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at system level.

HMC 2.0 Memory Controller ASIC IP Platform – Allows quick evaluation of the HMC technology and performance testing of the HMC links. Based on the Xilinx Virtex-7 FPGA, this platform includes a fully validated design that integrates HMC controller exerciser functions.

Interlaken IP – Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI.

Solutions:
Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+. The solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon’s IP fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die IO needed to drive the interface between the logic-die and the memory die-stack on the 2.5D Interposer.

Tech Talks:
Open-Silicon will present on following two topics in the conference:

  1. Topic:  “Role of 3rd Party IP Selection and Integration in ASICs”
    Time: 10:10
  2. Topic:  “Interlaken – High Speed Chip-to-Chip Interface IP supporting 1.2Tbps bandwidth and up to 56Gbps SerDes”
    Time: 15:00, Session 2b – From IP to SoC to System

Panel: 
IP Value on Programmable Devices or Embedded Programmable Blocks : Future and Vision
Moderator: Venkatesh Kumaran (IESA)
With the participation of:
Gabriele Saucier (CEO of D&R), Madhav Rao (Vice President, Engineering at Sankalp), Chris Dunlap (IP & Solutions Marketing Director at Xilinx), Abhijit Abhyankar (VP Silicon Engineering at FlexLogix), Naveen Narang (Sr. IP Application Engineer at Open Silicon), Sidhartha Mohanty (Director of the technology office at Intel)
Time: 16:00

WHEN:  Wednesday, April 5, 2017,
Time: 9:00a.m. – 5:00p.m.

WHERE: Hotel Park Plaza, 90/4,
Outer Ring Road, Marathahalli village,
Bengaluru, Karnataka 560037, India.

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system, software, IP – and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.  www.open-silicon.com

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Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions.  All other trademarks are the property of their respective holders.