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Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing Applications and Present on its Comprehensive IP Subsystem Solution for High-End Networking Applications at REUSE 2017…

Open-Silicon, a system-optimized ASIC solutions provider, will be exhibiting at REUSE 2017 in Santa Clara, CA on December 14, 2017. The company will demonstrate its comprehensive high bandwidth memory (HBM2) IP subsystem solution for 2.5D ASICs in FinFET technologies. This solution is targeted for high performance computing and networking applications. The company will also present on its comprehensive IP subsystem solution targeted for high-end networking applications.

Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in FinFET Technologies – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). The IP includes the controller, PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer. Open-Silicon’s HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high bandwidth data transfer rates of 1.6 Gbps/2Gbps, and interoperability between Open-Silicon’s HBM2 IP subsystem and HBM2 memory die-stack.

Comprehensive Networking IP Subsystem Solution Includes:

High Speed Chip-to-Chip Interface Interlaken IP – Open-Silicon’s 8th generation Interlaken IP core supports up to 1.2 Tbps high bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high bandwidth networking applications, such as routers, switches, Framers/MACs, OTN switches, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.

Forward Error Correction (FEC) IP – Open-Silicon’s FEC IP core significantly improves bandwidth by enabling 56G PAM4 SerDes integration. It can easily achieve a BER (Bit Error Rate) of <10-15 with an input BER of >10-6, which is required by most electrical interface standards using PAM4 SerDes. Built upon a flexible and robust architecture, Open-Silicon’s FEC IP core is compatible with various SerDes supporting different widths. The FEC IP is primarily intended to support the Interlaken interface, but can also be used to support different protocol controllers, resulting in significant area and power savings.

December 14, 2017, 9am – 6pm
Where: Exhibit Floor, Santa Clara Convention Center, Santa Clara, CA.

Presentation: Comprehensive IP Subsystem Solution for High-End Networking Applications
When: December 14, 2017

About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.  To learn more, visit

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.