Open-Silicon .:. Interlaken Core (High Speed Chip-to-Chip Interface)
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Want to get a budgetary quote for Interlaken ASIC? Please fill out the Design Requirements Form.


Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following
Interlaken Alliance specifications:

  • Interlaken Protocol Definition, v1.2
  • Interlaken Look-Aside Protocol Definition, v1.1
  • Interlaken Retransmit Extension, v1.2
  • Interlaken Dual Calendar Extension v1.0
  • Interlaken Interop Recommendations, v1.7

Designed and tested to be easily synthesizable into many ASIC technologies, the Open-Silicon Interlaken IP Core is uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.

Open-Silicon’s eighth-generation Interlaken IP core doubles user data bandwidth of the previous generation to 1.2 Tb/s by enhancing the SerDes and user interface support. This version of the IP core improves system reliability with the addition of Interlaken Retransmit Extension support. Building up on Open-Silicon’s robust and flexible architecture, the IP also adds support for multiple aggregate bandwidth interfaces within a single IP core instance, allowing for a more efficient implementation.

Key Features:

  • Fully-programmable SerDes lane mapping
  • Interlaken-LA 4-channel protocol
  • Up to 56 Gbps SerDes support
  • 1.2 Tbps high-bandwidth performance
  • Interlaken Retransmit Extension support

Standard Features:

In addition to the key features highlighted with the latest release, the Open-Silicon Interlaken IP also provides the following feature set as part of the standard IP functionality:

  • Support for 256 logical channels
  • 8-bit channel extension for up to 64K channels
  • Independent SerDes lane enable/disable
  • Support for SerDes speeds from 3.125Gbps to 56 Gbps
  • Configurable number of lanes from 1 to 48
  • Flexible user interface options:
    • 128b: 1x128b, 2x128b, 4x128b, or 8x128b
    • 256b:  1x256b, 2x256b, 4×256, or 8x256b
  • Programmable BURSTMAX from 64 bytes – 512 bytes
  • Programmable BURSTMIN from 32 bytes – 256 bytes
  • Simultaneous In-band and Out-of-Band flow control
  • Programmable calendar
  • Built-in error detection and interrupt structures
  • Configurable error injection mechanisms for test-ability

Want to get a budgetary quote for Interlaken ASIC? Please fill out the Design Requirements Form
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