Watch A Demonstration:
Watch a demonstration of the industry’s first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA and Open-Silicon IP.
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About Hybrid Memory Cube

Hybrid Memory Cube (HMC) is an innovative memory architecture that delivers unprecedented levels of performance in terms of bandwidth, power efficiency and reliability for networking and computing systems. Some of the benefits of HMC technology as compared to other memory technologies are:

• Provides 15x the performance of DDR3 module
• Utilizes 70% less energy per bit than DDR3 DRAMs
• 90% less space than today’s RDIMMs

About the HMC Consortium

The HMC Consortium is a working group made up of eight industry leaders who build, design-in, or enable Hybrid Memory Cube (HMC) memory technology. The goal of the Hybrid Memory Cube Consortium is to facilitate HMC Integration into a wide variety of systems, platforms and applications by defining an adoptable industry-wide interface that enables developers, manufacturers and enablers to leverage this revolutionary technology. The group works to innovate and expand the capabilities of the next generation of memory. Open-Silicon is a founding developer member of the Hybrid Memory Cube Consortium.
For more information, please visit http://www.hybridmemorycube.org/about.html

HMC Controller IP Core

Open Silicon’s HMC Controller IP provides the industry’s first, highest performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems.

As one of the developer member of the HMC Consortium, Open-Silicon plays a key role in developing the HMC interface specification and roadmap, as well as enabling industry application and ecosystem development. Open-Silicon’s HMC Controller IP is a high-performance and flexible soft macro implementation that can interface to Micron HMC Generation 2 devices. The IP provides system designers with the fastest and lowest risk solution for interfacing with Hybrid Memory Cube.

Features:
• Compliant HMC specification v1.1
• Interfaces to Micron HMC rev2 devices
• Fully synchronous, soft core implementation
• Supports HMC link operating at 10Gbps, 12.5Gbps, or /15Gbps
• Up to 4 HMC links managed by a single controller
• Up to 240 GB/s of total interface bandwidth
• Supports for half-width (8-lanes) and full-width mode (16-lanes)
• AXI 4.0 User Interface or Native User Interface
• Transaction, Link, and non-SerDes portion of Physical layer
• Parameterized number of user interface ports
• User interface ports have separate 256b, 512b, 768b or 1024b read and write paths
• Supports 16, 32, 48, 64, 80, 96, 112, and 128 byte requests
• Supports both posted and non-posted writes
• Supports HMC configuration and status access through mode read/write
• Support atomic and bit write requests
• Poison packet handling
• Scrambling and descrambling
• Power on initialization
• Power state management
• Error detection and automatic retry
• Warm reset
• Link Retry
• Link retraining
• Host recovery after link retry fails
• Token based flow control
• Response open loop mode
• Configurable error injection mechanisms for testability
• System Verilog assertions for user interface and configuration registers

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Download Brochure
For more information please contact ip@open-silicon.com

Xilinx HMC Controller IP Core

Optimized for Xilinx’s Virtex7 FPGA family, Open-Silicon’s HMC IP core is built to seamlessly interface with Xilinx GTH/GTX SerDes. Open-Silicon’s HMC Controller is highly configurable and supports a number of different implementation widths and user interface options allowing trade-offs between performance, utilization and clock frequency.

  • Compliant HMC specification v1.0
  • Interfaces to Micron HMC rev2 devices
  • Supports HMC link operating at 10 Gbps or 12.5Gbps
  • Up to 40GB/s of total interface bandwidth for single link 10Gbps SerDes
  • Up to 50GB/s of total interface bandwidth for single link 12.5Gbps SerDes.
  • Supports for half-width (8-lanes) and full-width mode (16-lanes)
  • AXI 4.0 User Interface or Native User Interface
  • Transaction, Link, and non-SerDes portion of Physical layer
  • Seamlessly integrates with Xilinx Virtex7 GTH/GTX SerDes
  • User interface ports have separate 512b, 768b or 1024b read and write paths
  • Supports 16, 32, 48, 64, 80, 96, 112, and 128 byte requests
  • Supports both posted and non-posted writes
  • Supports HMC configuration and status access through mode read/write
  • Support atomic and bit write requests
  • Scrambling and descrambling
  • Power on initialization
  • Power state management
  • Link retraining
  • Token based flow control
  • Response open loop mode

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For more information please contact ip@open-silicon.com

HMC Evaluation Board

Open-Silicon’s HMC evaluation platform is based on Xilinx Virtex7 XC7VX690T FPGA includes a fully validate reference design that integrates the HMC controller along with HMC exerciser functions. The HMC exerciser function along with the software stack allows for the quick evaluation of HMC technology and performance testing of the HMC links.

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HMC-Board

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For more information please contact ip@open-silicon.com