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Downloads: HMC ASIC IP Product Brief Xilinx FPGA HMC Controller IP Product Brief


Watch A Demonstration:
Watch a demonstration of the industry’s first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA and Open-Silicon IP.
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About Hybrid Memory Cube

Hybrid Memory Cube (HMC) is an innovative memory architecture that delivers unprecedented levels of performance in terms of bandwidth, power efficiency and reliability for networking and computing systems. Some of the benefits of HMC technology as compared to other memory technologies are:

• Provides 15x the performance of DDR3 module
• Utilizes 70% less energy per bit than DDR3 DRAMs
• 90% less space than today’s RDIMMs

About the HMC Consortium

The HMC Consortium is a working group made up of eight industry leaders who build, design-in, or enable Hybrid Memory Cube (HMC) memory technology. The goal of the Hybrid Memory Cube Consortium is to facilitate HMC Integration into a wide variety of systems, platforms and applications by defining an adoptable industry-wide interface that enables developers, manufacturers and enablers to leverage this revolutionary technology. The group works to innovate and expand the capabilities of the next generation of memory. Open-Silicon is a founding developer member of the Hybrid Memory Cube Consortium.
For more information, please visit http://www.hybridmemorycube.org/about.html

HMC Controller IP Core

The Open-Silicon HMC Controller IP is architected and designed to provide the highest performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems.

As a Developer Member of the HMC Consortium, Open-Silicon plays a key role in developing the HMC interface specification and roadmap, as well as enabling industry applications and ecosystem development.

The Open-Silicon HMC controller is a high-performance, flexible soft macro implementation that complies with v1.1 and v2.0 of the HMC protocol.

The IP is highly configurable with support for a number of different internal and user interface data path widths, allowing designers to tailor the controller to match their performance, area, or power requirements.

Key Features:

  • Transaction, link and logic sub-block of the physical layer
  • Seamlessly interfaces to leading third-party SerDes IP without the need for an additional PCS layer
  • Compliant with HMC specification v1.1 or 2.0; configuration register selectable
  • Support for 10Gbps, 12.5Gbps, and 15Gbps (HMC spec. v1.1)
  • Support for 12.5Gbps, 15Gbps, 25Gbps, 28Gbps, and 30Gbps (HMC spec. v2.0)
  • Support for half-width (8 SerDes lanes) and full-width (16 SerDes lanes) operation

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Download HMC ASIC IP Product Brief

For more information please contact ip@open-silicon.com

Xilinx HMC Controller IP Core

Optimized for Xilinx® FPGAs, the Open-Silicon HMC Controller IP is a high-performance, flexible soft macro implementation that complies with v1.1 of the HMC protocol.

The IP is highly configurable with support for a number of different internal and user interface data path widths and allows designers to tailor the HMC controller IP to match their performance or area requirements.

Key Features:

  • Transaction, link and logic sub-block of the physical layer
  • Seamlessly interfaces to Xilinx transceivers
  • Supports Xilinx Virtex®7, UltraScale™ Kintex® and Virtex FPGAs
  • Compliant with HMC specification v1.1
  • Support for 10Gbps, 12.5Gbps, and 15Gbps (HMC spec. v1.1)
  • Support for half-width (8 SerDes lanes) and full-width (16 SerDes lanes) operation

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Download Xilinx FPGA HMC Controller IP Product Brief

For more information please contact ip@open-silicon.com

HMC Evaluation Board

Open-Silicon’s HMC evaluation platform is based on Xilinx Virtex7 XC7VX690T FPGA includes a fully validate reference design that integrates the HMC controller along with HMC exerciser functions. The HMC exerciser function along with the software stack allows for the quick evaluation of HMC technology and performance testing of the HMC links.

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HMC-Board

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For more information please contact ip@open-silicon.com