Today’s products require more and more features and functionality to stand apart. As a silicon proven solution, Open-Silicon IP can be customized to enable further customer product differentiation. From the Interlaken high-performance chip-to-chip interconnect through SoC platform IP supporting different processor cores and peripherals, error-correction codes, compression engines, security and I/O controller IP solutions, Open-Silicon provides reliable high-quality IP solutions with a rapid path to silicon success.
IP listed here is available as stand-alone third-party IP, or as a part of the customizable system and physical design solutions offered by Open-Silicon.
Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following
Interlaken Alliance specifications:
Designed and tested to be easily synthesizable into many ASIC technologies, Open-Silicon’s Interlaken IP Core was uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.
Open-Silicon’s sixth-generation Interlaken IP core doubles user data bandwidth of the previous generation to 600Gbps by enhancing the SerDes and user interface support. This version of the IP core improves system reliability with the addition of Interlaken Retransmit Extension support. Building upon Open-Silicon’s robust and flexible architecture, the IP also adds support for multiple aggregate bandwidth interfaces within a single IP core instance, allowing for a more efficient implementation.
In addition to the key features highlighted with the latest release, the Open-Silicon Interlaken IP also provides the following feature set as part of the standard IP functionality:
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The SOCC-1110 is an 8051 based configurable SoC platform. The platform contains an 8051 CPU core, and all the peripheral functions required for a basic SoC.
The SOCC-1110 contains a single cycle 8051 CPU core plus standard set of SoC peripherals, including a system timer, a watchdog timer, an interrupt controller, programmable I/O, I2C Host, SPI master, real-time clock, alphanumeric LCD interface, 16550 UART and serial port. A memory controller supporting SRAM, Serial Flash, and Serial EERPROM also be optionally instantiated. The user also has the option to select from a library of cores and subsystems that have been pre-integrated and verified to work in this platform, including a DMA controller, 16450 UART, IDE Host, SATA Host and SATA Device interface. Also, 3rd party IP cores like JPEG decoders, TCP/IP hardware accelerators and Ethernet MACs can be easily integrated into this platform.
Many applications can be supported by this configurable platform including Home Area Networks (HAN), Smart Grid, Zigbee, wireless sensor networks, USB Flash Drives, USB IDE/SATA Drives, Web servers, Smart Card, Photo Frames etc.
The SOCC-1110 SoC platform may form the basis for a complete chip or it may also serve as a subsystem in a larger chip. Peripheral blocks may be added as needed, with the CPU and memory subsystems unaffected.
The example illustrated above features the SOCC-1110 core as a USB to SATA bridge. A USB core, SATA host controller, and DMA engine are added to the baseline platform to make it an end market driven platform.
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The SOCC-2110 is an 80251 based configurable SoC platform. The platform contains an 80251 CPU core, and all the peripheral functions required for a basic SoC.
The SOCC-2110 contains a single cycle 80251 CPU core plus standard set of SoC peripherals, including a system timer, a watchdog timer, an interrupt controller, programmable I/O, I2C Host, SPI master, real-time clock, alphanumeric LCD interface, 16550 UART and serial port. A memory controller supporting SRAM, Serial Flash, and Serial EERPROM also be optionally instantiated. The user also has the option to select from a library of cores and subsystems that have been pre-integrated and verified to work in this platform, including a DMA controller, 16450 UART, IDE Host, SATA Host and SATA Device interface. Also, 3rd party IP cores like JPEG decoders, TCP/IP hardware accelerators and Ethernet MACs can be easily integrated into this platform.
Many applications can be supported by this configurable platform including Home Area Networks (HAN), Smart Grid, Zigbee, wireless sensor networks, USB Flash Drives, USB IDE/SATA Drives, Web servers, Smart Card, Photo Frames etc.
The SOCC-2110 SoC platform may form the basis for a complete chip or it may also serve as a subsystem in a larger chip. Peripheral blocks may be added as needed, with the CPU and memory subsystems unaffected.
The example illustrated above features the SOCC-2110 core as a USB to SATA bridge. A USB core, SATA host controller, and DMA engine are added to the baseline platform to make it an end market driven platform.
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The 8051 CPU IP core is an instruction set compatible implementation of the MCS-51 family. The 8051 CPU IP core executes the instruction in a single clock cycle instead of the original 12 cycles per instruction execution time. The program memory has been increased to 256Kbytes, and RAM has been increased to 256 bytes. The I/O ports of the IP core have been simplified by removing unnecessary muxing on the ports to make it fully compatible with today’s system on chip (SoC) design practices.
The 8051 CPU has been designed for integration into SoC based designs. Numerous standard peripherals can be integrated to the 8051 CPU IP core by using the AMBA interface.
The 8051 CPU IP core platform can be integrated with numerous silicon proven peripherals developed by Open-Silicon or other third party vendors to form a complete chip level solution. The 8051 CPU IP core can be used in various application areas
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The 80251 CPU IP core is an instruction set compatible implementation of the MCS-251 family. The 80251 core executes the instruction in a single clock cycle, and is on average about 3.19 times faster than the original implementation. The performance improvements are due to architectural enhancements done to the CPU core. The I/O ports of the IP core have been simplified by removing unnecessary muxing on the ports to make it fully compatible with today’s system on chip (SoC) design practices.
The 80251 CPU has been designed for integration into SoC based designs. Numerous standard peripherals can be integrated to the 80251 core by using the AMBA interface.
The 80251 IP core platform can be integrated with numerous silicon proven peripherals developed by Open-Silicon or other third party vendors to form a complete chip level solution. The 80251 IP core can be used in various application areas:
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The SOCP-1010 is a completely integrated subsystem of infrastructure IP that is pre-verified and integrated with all basic peripheral functions to enable any system on chip (SoC) design. Additionally Open-Silicon can further customize or configure this subsystem of IP based on customer requirements. This infrastructure subsystem IP is inherently processor independent and currently supports MIPS, ARC, ARM, Tensilica embedded processor cores. Other processor cores like PowerPC and DSP can easily be integrated.
The SOCP-1010 contains a standard set of SoC peripherals, including a system timer, a watchdog timer, an interrupt controller, programmable I/O, I2C Host, SPI master, 16550 and 16450 UARTs, real-time clock and an optional high-bandwidth memory controller supporting Flash, SRAM, SDRAM or DDR2/3 can also be optionally instantiated. The user also has the option to select from a library of cores and subsystems that have been pre-integrated and verified to work in this platform, including an IDE Host, SATA Host and SATA Device interface. Also, 3rd party IP cores like decoders, Gigabit Ethernet MACs, and 802.11a, 802.11b or 802.16 wireless MACs or others can be easily integrated into this platform.
Many applications can be supported by this configurable platform including MIMO mobility devices, Access Point controllers for Network Security Processors, Home Gateways, DVD players, Network routers, Set-top boxes, Storage Area Network controllers, Network Attached Storage devices, etc.
The SOCP-1010 SoC Infrastructure Subsystem may form the basis for a complete chip. It may also serve as a subsystem in a larger chip. Peripheral blocks may be added as needed, with the CPU and memory subsystems unaffected.
The example illustrated above features the SOCP-1010 subsystem IP core as an enhanced system for use in a hand-held organizer. A processor, LCD interface, PC Card interface and IrDA controller are added to the basic system.
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The DDRC-1010 Shared Memory Processor provides a flexible interface to external Double Data Rate Synchronous DRAM (DDR DRAM) memories. It includes a configurable arbitration unit and an available arbitration watchdog timer. The DDRC-1010 has a single control port for configuration; control and status register access, and can be configured to support multiple concurrent channels. A dedicated CPU channel is provided to minimize CPU latency. Data width can be 32-bit or 64-bit.
The DDRC-1010 can be configured for up to 4 external memory banks. Each external memory bank can access up to 1 GB of memory, and is memory-mapped with configurable address decodes. Each bank has independent programmable timing controls, and can be configured to support either 32-bit or 64-bit data widths.
The DDRC-1010 supports 400 MHz IP core operation (800 Mbps), and can interface to AMBA buses.
The DDR DRAM Shared Memory Processor provides memory access to a number of off-chip memories for multiple requestors. All accesses are arbitrated and decoded from memory-mapped addresses by the Shared Memory Processor.
The example above shows a system with a Von Neumann architecture CPU (host processor) and Harvard architecture DSP, and a number of DMA peripheral interface blocks. This is a standard configuration for systems with shared memory. In the illustration, each memory requestor has an AXI interface; the Shared Memory Processor arbitrates internally between all requestors. A single APB interface allows the CPU to configure and control the memory processor and the external memories. An optional interrupt is available to alert the processor of a watchdog timeout, if desired. The memory processor controls access to multiple banks of DDR/DDR2 DRAM, providing fast access to large amounts of buffer memory. A second Flash/SDRAM Shared Memory Processor provides access to Flash for processor boot-up; it is isolated so that its low performance does not impact the DDR throughput, and because of the electrical differences between the interfaces.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The FSDM-1010 Multi-port Memory Controller provides a flexible interface to external Single Data Rate Synchronous DRAM (SDRAM) and asynchronous memories such as Flash and SRAM. It can arbitrate between up to 8 DMA requesters, with configurable arbitration and an available arbitration watchdog timer. The FSDM-1010 can be configured for up to 8 external memory banks. Each external memory bank can access up to 512 MB of memory, and is memory-mapped with configurable address decodes. Each bank has independent programmable timing controls, and can be programmed to support either 16-bit or 32-bit data widths.
The SDRAM controller incorporates automated SDRAM initialization, auto-refresh, self-refresh, and open bank management. The SRAM/Flash controller has pin- and register-configurable bus width controls, and includes facilities for a wait/ready signal for interfacing to peripheral devices.
The FSDM-1010 supports up to 166 MHz operation with 0.18-micron technology, and is available with interfaces to ARM’s AMBA buses.
This product can be integrated into the PF-1000 Open-Silicon SoC Platform as a library component.
The Flash/SDRAM Multi-port Memory Controller provides access for multiple requestors to a variety of off-chip memories. All accesses are arbitrated and decoded from memory-mapped addresses by the shared memory processor.
The example above shows a system with a Von Neumann architecture CPU (host processor) and Harvard architecture DSP, and a number of DMA peripheral interface blocks. This is a standard configuration for systems with shared memory. In the illustration, each memory requestor has an AHB interface; the Multi-port Memory Controller arbitrates internally between all requestors. A single APB interface allows the CPU to configure and control the memory processor and the external memories. An optional interrupt is available to alert the processor of a watchdog timeout, if desired. The memory processor also controls access to multiple banks and multiple types of memories, including Flash, SRAM and SDRAM. The physical connection to these memories may vary with the system’s requirement, but may include, for example, a single bank of 16-bit boot Flash, a single SDRAM-like device, and 4 banks of 32-bit SDRAM modules.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The LCDC-1010 is designed to communicate and control 4 and 8-bit character LCD devices. Primarily, LCDC-1010 is designed to support Hantronix character LCD devices but its programmable registers make it compatible with various LCD formats through different combinations. The LCDC-1010 is capable of handling two back-to-back data write transfers to the device but it can handle only single data read transfer from device.
The LCDC-1010 is designed to connect to the AMBA bus, and can interface to most system buses. It can be integrated into the SOCP-1010 Open-Silicon SoC Platform as a library component.
The LCDC-1010 can be used in embedded systems to display information on LCD device in the form of text and small icons. The character LCD display are specifically designed for displaying basic text which makes it less expensive, less complex and easier to use. Character LCD displays come in various sizes, color, and background, and through the control interface of this IP core the LCD display can be reprogrammed to switch between various font sizes and colors.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The ISO7816 Smart Card Interface IP core is a specialized UART, designed to meet specific ISO/IEC 7816-3 protocol requirements. Its flexibility can be tailored to meet T=0, T=1 and T=2 transmission protocols. The ISO7816 Smart Card Interface is designed to connect to the AMBA bus and can be interface to most peripheral expansion buses.
The ISO7816 Smart Card Interface provides a communication interface with the contacts of a smart card. It may be used with an analog module for contacted (card inserted into reader) and contact-less (wireless) operation, or can be used stand-alone for a contacted interface only.
Smart Cards can be used for a variety of transactions, including credit/debit cards, access cards and “virtual shopping carts”. They provide the same convenience of conventional magnetic-stripe cards with much higher data capacity, available security features, and capability to update information on the card.
The example above features all connections needed to integrate the Smart Card controller into a Smart Card reader SoC. The CPU transfers data to and from the Smart Card via the APB interface. Once the programmable FIFO threshold has been reached, the Smart Card controller interrupts the CPU. If an analog interface controller is added to the system, two mode signals are provided to handshake between the two modules.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The RTC-0110 implements the functionality of a standard Real-Time Clock (RTC), and can be integrated into system on chip (SoC) designs. RTC is a collection of synchronous counters and comparators that allows the host processor access to the current time of day. Alarms may be set and activated through the host firmware to start or stop various processes at different times and intervals.
The Real-Time Clock requires a separate 32.768Khz input clock. The 32.768 KHz clock is divided down to generate a 1 Hz clock that drives the seconds register. The other timer registers (minute, hour, day, etc.) update as appropriate on each 1 Hz clock pulse.
A separate timer that runs off of the 32.768 KHz clock is provided to generate a periodic interrupt to wake the processor when the primary system clock is disabled. This product can be integrated into SOCP-1010 Open-Silicon SoC Platform as a library component.
The RTC-0110 IP core can be integrated into any ASIC/SoC solution, and this solution can be used in various embedded systems to maintain the correct time of a system. A real-time clock runs of a special battery power which is different than the normal power supply of the system to keep track of the system time; even when systems are powered off. For example the RTC based ASIC/SoC can be used in digital video and still cameras, to maintain the time of the system, and print the current time on photographs or video.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The UART-1011 IP core is functionally compatible with the 16450 and 16550 standard UART devices. The IP core functions as an asynchronous serial data input/output interface for system on chip (SoC) designs, performing serial/parallel conversion on data characters to and from a serial device. The UART-1011 includes a programmable baud rate generator and edge detector. The transmitter and receiver are each buffered with a 16 byte FIFO to reduce the CPU overhead. The IP is designed to connect to the AMBA APB bus or any on-chip peripheral bus. The data transfer is initiated via the AMBA APB interface. An interrupt is generated upon the completion of data transfer. It can be integrated into the SOCP-1010 Open-Silicon SoC Platform as a library component.
The UART-1011 IP core is used to communicate between a computer’s interface and its serial devices. This includes terminals, modems or other peripheral devices such as scanners, mice, or keyboards that support asynchronous serial data transfers. It can also be used in custom applications such as handheld PCs. The UART modem control and status signals can be used for software flow control. It can also be used as a debug interface, in any SoC design. The above example features the IP core integrated into a SoC environment. The UART interface communicates to the PC through an RS-232 cable.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The URTL-1010 functions as an asynchronous serial data input/output interface for system on chip (SoC) designs, performing serial/parallel conversion on data characters to and from a serial device. The URTL-1010 IP core is derived from the standard UART device, and is optimized for low gate count while retaining the most commonly used functions.
Because of its small size relative to the 16550 UART, the URTL-1010 is ideal for system monitoring, self-test and debug. The URTL-1010 is designed to connect to the AMBA bus and can interface to most peripheral expansion buses.
The UART-Lite IP core is used to communicate between a computer’s interface and serial devices such as terminals, scanners, pointing devices and keyboards that support asynchronous serial data transfers. It can also be used in custom applications such as handheld PCs. The UART-Lite is register-set compatible with the 16450 UART but without modem support, making it ideal for system monitoring and debug, and for devices which require standard asynchronous communication with a minimal die size.
The above example features the UART-Lite IP core integrated into an SoC environment. The UART interface communicates to the PC through an RS-232 cable. Direct control of the data transfer is initiated through the APB controller. An interrupt is asserted at the completion of each data transfer.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The URTS-1012 functions as an asynchronous serial data input/output interface for system on chip (SoC) designs, performing serial/parallel conversion on data characters to and from a serial device. The URTS-1012 IP core is derived from the standard UART device, and is optimized for low gate count while retaining the most commonly used functions. This IP core is capable of autobaud/autoformat detection, and supports hardware/software data flow control.
Because of its automatic hardware/software flow control features and DMA capability, the URTS-1012 is ideal for communication systems. The DMA interface enhances system performance by off-loading the processor when transferring large amounts of data. The URTS-1012 is designed to connect to the AMBA bus and DMA channel interfaces, and can interface to most peripheral expansion buses.
The SmartUART IP core is used for communication between a computer and different peripheral devices. These would include serial devices such as terminals and modems, or other peripheral devices including scanners, mice and keyboards that support asynchronous serial data transfers. It can also be used in custom applications, such as handheld PCs. The SmartUART modem control and status signals can be used for automated software/hardware flow control of data to and from system memory. The combination of hardware support for flow control and DMA to memory is especially useful for transferring large blocks of data with minimal processor intervention.
The above example features the SmartUART IP core integrated into an SoC environment. The UART interface communicates to the PC through an RS-232 cable. Direct control of the data transfer is initiated through the CPU interface. Data can be transferred via the CPU or directly to memory via the DMA interface. An interrupt to the CPU is asserted at the completion of the data transfer.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The I2CM-1010 Serial I2C master is designed to support serial interfaces with various I2C-compliant devices. It allows firmware to configure the serial I2C interface to different modes to support a number of external serial peripheral devices. The I2C master is designed to support 8-bit devices. Address and device address width are programmable. Transfers can also be single-byte and burst transfers.
All transfer protocols required for I2C operation are performed automatically by hardware, including the two-way acknowledgment of data character receipt by the external device and the I2C master. The I2C master does not support multi-master arbitration or device wait.
The I2C interface provides support for a high data rate interface with a low pin count. The I2C master acts as an interface between an embedded CPU and external I2C peripheral devices. Such devices include flash memory, or other ASICs and ASSPs. The interface acts the interface master, initiating data transfers to and from the peripheral device.
The example above shows the I2C master core used to interface to serial flash. This application is commonly used to store device configuration data to a removable media card. Example applications include cell phones and game controllers. The I2C master communicates to the flash through two bi-directional pins. The APB interface is used for CPU control of the I2C core. When data transfer is complete, an interrupt is generated to the interrupt controller; the CPU reads the status of the block and services the interrupt.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The I2MS-1011 is designed to support serial interfaces with various I2C-compliant hosts and devices. The I2MS-1011 can be configured to operate either in master or slave mode. The IP core is designed to support an 8-bit data bus with single or bursts transfers based on the data size configured in the control register. All transfer protocols required for I2C operation are performed automatically by hardware, including the two-way acknowledgment of data character receipt. The IP core supports multi-master arbitration, and the arbitration success or failure is indicated through a status bit.
The I2MS-1011 is designed to connect to AMBA bus, and it can interface to most peripheral expansion buses. The IP core can be integrated into the SOCP-1110 Open-Silicon SoC Platform as a library component.
The I2C interface provides support for high data rate transfers with low pin count. The I2MS-1011 acts as an interface between embedded processors and external I2C peripheral devices. Such devices include EEPROM memories, ASICs and ASSPs. While operating in master mode, the I2MS-1011 initiates data transfers to and from the peripheral devices. Whereas, in slave mode, the I2MS-1011 responds to the master’s requests with acknowledgments and 8-bit data that is requested by master.
The above example shows the I2MS-1011 IP core being used to interface to a serial EEPROM. This type of application is commonly used to store device configuration data, and is commonly used in cell phones and game controllers. The I2MS-1011 communicates to the EEPROM through the two bi-directional pins, and the CPU controls the I2MS-1011 through the MBA bus. When data transfer is complete, an interrupt is generated to the interrupt controller; and the CPU services the
interrupt.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The SPFL-1010 Serial Flash Controller is designed to support serial flash memories in a system. The flash controller supports the SPI modes 0 and 3, which are the most commonly used modes in flash devices. The flash controller translates the read command from the AMBA bus or any other on chip bus into a read command to the flash device, and provides the required data to the on-chip requestor.
The SPFL-1010 can be used to erase and reprogram the flash device. The CPU can program the required configuration and control registers in the controller through AMBA bus to execute an ERASE, PROGRAM or WRITE command to the device. The IP core will then generate the required cycles to the device. In addition any other control commands such as read ID, status, etc. can also be issued in the same manner.
The SPFL-1010 is designed to connect to AMBA or any other on chip buses, and can be integrated into the SOCP-1010 Open-Silicon SoC Platform as a library component.
The SPFL-1010 can be integrated in ASIC/SoC/FPGA based solutions, to provide access to non-volatile memory in a system. This memory can then be used to store either system specific information, or to use it as boot memory. The use of a serial device reduces the pin count in a system, while providing the required performance. The SPFL-1010 offloads the CPU from control of data transfer to/from serial flash memory, which in turn increases the overall memory subsystem performance.
As shown in the above diagram the CPU is booting up from an off chip SPI flash memory while using the SPFL-1010.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The AESE-1010 is a dedicated hardware accelerator that performs the cipher/decipher function on the incoming data. The AESE-1010 supports both PIO and DMA mode of operation. The AESE-1010 supports the three AES key sizes 128, 192, 256-bit, and performs offline key expansion. It supports AES ECB, CBC, CTR and CCM modes of operation and is fully compliant with IEEE 802.16e and ZigBee specifications for CTR and CCM modes.
The AESE-1010 is designed to interface to the host processor through the AMBA APB interface and to memory through a DMA channel. It can interface to most peripheral expansion buses.
The AES accelerator is used to encrypt and decrypt data. The AES accelerator is applicable to any system that needs to provide hardware acceleration for the purposes of encryption and decryption of data such as storage, 802.16 MAC layer, TCP/IP stacks, security and surveillance.
The example above shows the AES controller being used in a secure solid state storage device.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The HASH-1010 is a dedicated hardware accelerator that calculates the hashing function (or the message digest) for given byte oriented data or message. The HASH-1010 supports both PIO and DMA mode of operation. The HASH-1010 implements the most widely used hashing algorithms SHA-1, SHA-2(256) and MD5 in a single IP core. The support for the multiple modes makes the SHA engine particularly suitable for implementation of internet security protocols, such as IPSec that requires multiple authentication algorithms. The input data is padded according the specific requirement of the hashing algorithm and endian-conversion is performed in the hardware.
The HASH-1010 is designed to interface to the host processor through the AMBA interface and to memory through a DMA channel. It can interface to most peripheral expansion buses.
SHA Engine functions such as SHA-1, SHA-2(256) and MD5 are extensively used in digital signatures, on-line banking, electronic fund transfer and electronic data transfer authentication applications.
The example above shows the SHA engine being used in an IPsec offload hardware engine.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The LZW compressor encodes strings by reference to a dynamically generated dictionary. It exploits the redundancy of data for efficient compression by compressing uses up to 13 bit codewords. Each entry in the dictionary is a string and it is initialized with every possible byte by storing the byte in a 16384 entry two way skewed cache structure and as each entry is a 25 bit value it creates the hash table with 51200 bytes.
This is implemented as four 4K x 25 bit single port RAM along with a two way skewed cache structure which also includes a pair banked RAM for emulating a two port RAM.
The de-compressor unit decompresses the incoming data stream by using a dictionary size of 8192 locations. It shares the dictionary RAM with compressor. It also uses the compressor’s data RAM to store character strings, and the compressor’s compressed data RAM to store string tracking information.
Some of the applications domain where LZW utilized is given below:
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The Bose-Chaudhuri-Hochquenghem (BCH) Error Correcting Code (ECC) is a complete BCH Encoder and Decoder IP core that is implemented over GF(13). The IP core includes two independent units, a parallel BCH Encoder for the generation of the BCH code and an independent BCH Decoder IP core based on Syndromer, Berlekamp-Massey, Chien Search and Error Correction units. The encoder and all the decoder units can be used separately or together.
The interface provided on the BCH Encoder & Decoder is generic and can be easily combined with any type of chip point-to-point buses. Open-Silicon also provides the AMBA bus interfaces that can be easily used with the BCH Encoder and BCH Decoder IP cores.
BCH codes are used in wide range of applications from digital communications to storage, some of them are:
The above example features the BCH IP core integrated with a NAND Flash Controller to manage the inherent soft and random errors, as well as burst errors in MLC/SLC NAND Flash devices. The BCH IP core can be used to detect and correct multiple errors.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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Open-Silicon I/O controllers consists of storage controllers, ECC (error-correcting codes) and compression engines. The IP can be used for both solid state and rotating media. The IP offering is highly-configurable and can be customized to meet area/performance requirements. The IP blocks can be used as a stand-alone point solution or used as part of Open-Silicon customized and verified storage system on chip (SoC) solution.
Available I/O Controllers
The SATD-1110 is designed to interface between a host system and a storage controller, either solid state or rotating media. The Serial ATA IP core decodes incoming host commands and sets up the proper interrupts and status for the local microprocessor to handle ATA and ATAPI commands. Data transfer commands can be automated for full data transfer with minimal firmware support. The IP core can be programmed for full automation or full firmware handling of each phase of command handling. The SATD-1110 provides a FIFO interface to an external DMA controller for integration into systems with custom DMA functionality, such as an automated cache controller.
The SATD-1110 has two system interfaces: a control interface and an interface to an external DMA controller. The SATD-1110 product supports the AMBA bus interface. This IP core connects to an external DMA controller via a FIFO interface.
The Serial ATA target IP core connects a Serial ATA storage device to a host system, with command interpretation handled by the target IP core in conjunction with an embedded processor.
The example above shows the Serial ATA target IP core integrated into a solid-state drive. The Serial ATA target connects to the host system via a connector. Command processing is performed by interrupting the embedded processor; the processor parses the command and configures the various components to handle the command. Data is transferred through the ATA target IP core into a data buffer via a DMA engine. ECC is calculated for the data and it is stored to the media under software direction. Data is read from the media, corrected via ECC if necessary, and transferred from the buffer to the host via the Serial ATA IP core.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The SATH-1111 Serial ATA host interface IP core provides an efficient and easy-to-use interface to Serial ATA (SATA) devices. The IP core implements transfer speeds of 150 MB/s, and emulates programmable I/O, multi-word DMA, and Ultra ATA modes of operation. The IP core can be configured as a primary or secondary IDE controller, and emulates master/slave operation for support of up to two devices. The IP core interface to the SOC includes a DMA controller to optimize data transfers to and from the IDE devices, and provides PIO access via shadow registers. For ease of integration, the SATH-1111 includes a register set that is compatible with the Intel chip set.
The SATH-1111 has two system interfaces: a control interface and an interface to an external DMA controller. The SATH-1111 product supports the AMBA bus interface. This IP core connects to an external DMA controller via a FIFO interface.
The SATA Host IP core is used to control Serial ATA drives. The Serial ATA Host is applicable to any system utilizing IDE/ATA protocol with Serial ATA drives for data storage including desktop computers, servers, set-top boxes and test equipment.
The example above shows the Serial ATA Host controller in a PCI I/O chip for use in a personal computer. The application supports two floppy drives, two Serial ATA drives and two IDE/ATAPI drives. The Serial ATA host controller is configured as a primary port controller; the IDE Host controller is configured as a secondary port controller. The IP core’s DMA channel interfaces are connected to the PCI bus via an arbiter.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The ATAP-6010 is designed to interface between a host system and a storage controller, either solid state or rotating media. The ATA block decodes an incoming host command and sets up the proper interrupts and status for the local microprocessor to handle various ATA commands. Many commands can be automated for full data transfer with minimal firmware support. Options also exist for full firmware handling of each phase of command handling. The ATAP-6010 includes advanced features such as Ultra-ATA support and support for very large storage devices.
The ATAP-6010 is designed to interface to the local processor through the AMBA APB interface and to a data buffer memory through a separate DMA channel.
The ATA target IP core connects an IDE storage device to a host system, with command interpretation handled by the target IP core in conjunction with an embedded processor.
The example above shows the ATA target IP core integrated into a solid-state storage device – a flash card. The ATA target connects to the host system via a connector. Command processing is performed by interrupting the embedded processor; the processor parses the command and configures the various components to handle the command. Data is transferred through the ATA target IP core into a data buffer via a DMA engine. ECC is calculated for the data and it is stored to the media under software direction. Data is read from the media, corrected via ECC if necessary, and transferred from the buffer to the host via the ATA IP core.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The UIDE-4010 IDE host interface IP core provides an efficient and easy-to-use interface to IDE and ATAPI devices. The IP core implements programmable I/O, multi-word DMA, and Ultra ATA-33, -66, -100 and -133 modes of operation and supports up to two devices. The IP core interface to the system on chip (SoC) provides PIO access and DMA capability to optimize data transfers to and from the IDE devices. For ease of integration, the UIDE-4010 includes a register set compatible with the Intel chip set, including a descriptor-based scatter-gather DMA IP core. This IP core is compatible with ATA-4 with Ultra ATA-33, -66, -100 and -133 extensions.
The IDE Host block is used to control IDE disk drives. The IDE Host is applicable to any system utilizing IDE/ATA and ATAPI drives for data storage including notebook and desktop computers, servers, set-top boxes and test equipment. It is suitable for use with all form factor IDE/ATA and ATAPI drives.
The example above shows the IDE Host block used in a PCI I/O chip for use in a personal computer. The application supports four drives by instantiating two IDE Host controller blocks; one controller is configured as a primary port controller; the second controller is configured as a secondary port controller. The IP core includes a scatter-gather DMA channel compatible with the Intel scatter-gather DMA engine.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The ATAH-1110 CE-ATA host controller IP core provides an efficient and easy-to-use interface to CE-ATA devices. The CE-ATA host controller provides both PIO and DMA mode for data transfer. The DMA controller can be used where high bandwidth and low CPU overhead is required. While designs that are targeted for low bandwidth applications, users can optionally remove the DMA controller and just use PIO mode thus saving on gate count. The host controller also provides a proprietary clock speed controlling feature which can be used to control data transfer rates dynamically when a CPU is not in a position to service regular data transfer rates.
The ATAH-1110 is designed to interface to the host processor through the AMBA APB interface and to memory through a DMA channel. It can interface to most peripheral expansion buses.
The CE-ATA Host block is used to control CE-ATA disk drives. The CE-ATA Host is applicable to any system utilizing CE-ATA drives for data storage, including notebook and desktop computers, set-top boxes, flash drives, cameras, MP3 players, security and surveillance.
The example above shows the CE-ATA Host block used in a PCI I/O chip for use in a personal computer. A single DMA block and an APB Controller block provide access paths to the drives. These blocks interface to a PCI block for connection to the host PCI bus.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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The ATAD-1110 CE-ATA device controller IP core provides an efficient and easy-to-use interface to CE-ATA Host. The CE-ATA device controller provides both PIO and DMA mode for data transfer. The DMA controller can be used where high bandwidth and low CPU overhead is required. While designs that are targeted for low bandwidth applications, users can optionally remove the DMA controller and just use PIO mode thus saving on gate count. The MMC device registers (OCR, CID, CSD, EXT_CSD, RCA, and DS) are implemented in hardware. The CE-ATA MMC command 60 and 61 are implemented.
The ATAD-1110 is designed to interface to the host processor through the AMBA APB interface and to memory through a DMA channel. It can interface to most peripheral expansion buses.
The CE-ATA target IP core connects a CE-ATA storage device to a host system, with command interpretation handled by the target IP core in conjunction with an embedded processor.
The example above shows the CE-ATA target IP core integrated into a solid-state drive. The CE-ATA target connects to the host system via a connector. Command processing is performed by interrupting the embedded processor; the processor parses the command and configures the various components to handle the command. Data is transferred through the ATA target IP core into a data buffer via a DMA engine. Data is encrypted and ECC is calculated on the data and it is stored to the media under software direction. Data is read from the media, corrected via ECC if necessary, decrypted and transferred from the buffer to the host via the CE-ATA IP core.
The IP core deliverable includes RTL code, synthesis scripts, test benches, and verification test suites.
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Open Silicon’s HMC Controller IP provides the industry’s first, highest performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems.
Open-Silicon’s HMC Controller IP is a high-performance, flexible soft macro implementation of the Micron HMC Generation 2 Interface Protocol. The design provides system designers with the fastest, lowest risk solution for interfacing to the Hybrid Memory Cube.
The Open-Silicon HMC IP supports the Micron HMC Generation 2 Interface. As one of the developer members of the HMC Consortium, Open-Silicon plays a key role in developing the HMC Interface Specification and roadmap, as well as enabling industry application and ecosystem development.
Designed and tested to be easily synthesizable into 45nm – 22nm ASIC technologies, Open-Silicon’s HMC IP Core was uniquely built to seamlessly interface with SerDes from leading technology vendors. This allows Open-Silicon customers to quickly integrate the HMC IP Core into their process technology and SerDes vendor of choice.
Some of the prime benefits of HMC Technology as compared to other memory technologies are:
The HMC Consortium is a working group made up of industry leaders who build, design-in, or enable Hybrid Memory Cube (HMC) memory technology. The group works to innovate and expand the capabilities of the next generation of memory-based. For more information, please visit: http://www.hybridmemorycube.org/
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The 40Gb PCS is a 40Gb/s Physical Coding Sublayer (PCS) to be used in high port density switching ASICs. The 40Gb PCS interfaces to four 10G SERDES as well as a MAC and provides PCS functionality with low gate count thus providing both area and power savings. The 40Gb PCS is compliant with 802.3ba clause 82 for 40Gbps (802.3-2008 clause 49 specifies 10Gb PCS of which 40G is a natural extension) operation. The 40G PCS is architected for both ASIC and FPGA implementations.
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The 40G Ethernet Media Access Controller (MAC) implements essential protocol requirements for operation of 40 Gbp/s Ethernet (IEEE 802.3ba) compliant node. The 40GMAC IP Core supports configurable FIFO’s on both transmit and receive side to handle application’s latency during the frame transmission and reception. The 40GMAC is compliant to IEEE 802.x standard for full-duplex operations by supporting PAUSE frame and PAUSE operations. The 40G MAC is architected for both ASIC and FPGA implementations using a standard tool flow.
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The 100G PCS is a 100 Gb/s Physical Coding Sublayer (PCS) to be used in high port density switching ASICs. The 100Gb PCS interfaces to ten 10G SerDes as well as MAC and provides PCS functionality with low gate count thus providing area and power savings. The 100Gb PCS is compliant to 802.3ba clause 82 for 100 Gbps (802.3-2008 clause 49 specifies 10Gb PCS of which 100G is a natural extension) operation. The 100G PCS is architected for both ASIC and FPGA implementation using a standard tool flow.
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The 100G Ethernet Media Access Controller (MAC) implements essential protocol requirements for operation of 100 Gbp/s Ethernet (IEEE 802.3ba) compliant node. The 100GMAC IP Core supports configurable FIFO’s on both transmit and receive side to handle application’s latency during the frame transmission and reception. The 100GMAC is compliant to IEEE 802.x standard for full-duplex operations by supporting PAUSE frame and PAUSE operations. The 100G MAC is architected for both ASIC and FPGA implementations using a standard tool flow.
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The DDRC-3010 is a high performance memory controller that provides a highly configurable interface to external Double Data Rate Synchronous DRAM (DDR3 DRAM). It can support up to 8 AXI User ports with an intelligent scheduler that is optimized for very high throughput. It also includes a CPU port that is optimized for low latency and timing critical transactions. DDRC-3010 can support data rates up to 2133 Mbps.
The DDR3 memory controller can support a wide variety of memory devices and organizations including standard DDR3 DIMMs like UDIMM, RDIMM, etc. The memory controller supports all the memory functions including automated initialization, self-refresh, auto-refresh and power-down etc. The various DDR3 timing parameters are programmable. It can be configured to optionally support ECC, command /address parity and 1T/2T timing.
The DDR3 memory controller has a highly intelligent scheduler that includes multiple algorithms to improve the memory throughput. The scheduler improves the memory throughput by reordering requests and minimizing the effects of various DDR internal operations like precharge/refresh, etc. The controller can support BL8 (burst length) or BC4 (burst chop) on-the-fly to improve memory throughput.
The memory controller supports DDR PHY Interface (DFI v2.1) to ease the integration of DDR PHY. It supports the DFI frequency ratios of 1:2 and 1:4.
The DDR3 controller is highly configurable solution and can be targeted towards a wide variety of applications such as:
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