Moore’s Law tells us that digital transistor density is doubling every two years. However, these foundry process advances no longer provide us with the same process-driven gains in the areas of power and performance. Also, these new technologies have definite limitations in transistor leakage and the ability to tightly control the process variability. And yet customers still need to build the best possible custom silicon to gain an advantage in the marketplace.
The EDA community, alongside the wafer foundries and process equipment manufacturers, have worked hard to address these limitations with improved methodologies and new sophisticated forms of analysis. However, while these EDA toolsets are common across the IC design landscape, they can be substantially improved upon.
Open-Silicon’s MAX Technologies represent patented and proven design technology to increase processor performance, lower design power, and manage process variability through post-silicon compensation techniques. Using a design-specific library augmentation, Open-Siliocn creates new cells, called ZenCells™ that are used for improving power and speed.
PowerMAX focuses on lowering design power, in particular leakage power. The advent of High K Metal Gate technology has allowed us to resume scaling the gate voltage without fear of gate leakage, leaving subthreshold leakage as the undisputed king of battery drain in today’s mobile devices.
Open-Silicon offers the experience from almost 100 processor hardenings including: ARM, MIPS, PowerPC, Tensilica, ARC, Customer Proprietary, and DSP.
Open-Silicon’s CoreMAX focuses on two areas for processor performance enhancement:
Open-Silicon 65nm test chip silicon results are shown to right. Note that some devices burn more power from leakage than they do from dynamic power, while others leak very little at all. A couple of the devices burn 300mW with the clock off, while others burn only 200mW while running 580MHz. This is the deep submicron variability problem.
The VariMAX technology uses post-silicon compensation schemes to reduce power, improve yields, and potentially increase performance.
PowerMAX™ enables design for the lowest possible power. Low power design has moved to the mainstream with 90nm, 65nm, and 40nm, as even designs that were not traditionally power sensitive are now paying close attention to power consumption due to exponential growth in leakage power and higher dynamic power from increasing levels of integration and performance.
In implementing low power designs, Open-Silicon starts with a robust design methodology using conventional techniques. These power savings methods include low-power place-and-route, voltage islands, power gating, clock gating, multi-Vt, and multi-channel length. Some of these techniques have been around for years, while
some, such as multi-channel length, are relatively new.
Also, some designs will require use of a few techniques, while others may need them all to achieve their market goals. Open-Silicon’s design teams work with our customers to explore the power savings potentials and implementation costs of each, so that the right solution can be put together.
These conventional techniques are shown in the diagram to right:
PowerMAX adds to this foundation with four new technologies: transistor level transformations, back biasing, power recovery, and custom leakage signoff. This results in the ASIC industry’s most complete low power design offering:
PowerMAX’s transistor level optimization creates new standard cells on-the-fly, called ZenCells™, to drive down both dynamic and leakage power. In addition to its variability control value, back biasing can also be employed whenever devices enter standby mode to further throttle back leakage power and prolong battery life. Power recovery operates late in the design phase to find timing paths with extra timing margin and replace cells with either higher Vt or lower drive strength equivalents. Finally, with custom leakage signoff Open-Silicon characterizes cell library leakage throughout the temperature range and then uses the actual design junction temperature for the leakage power calculation. Since the leakage power doubles every 15 degrees C, this is required for accurate power estimation.
The complete Open-Silicon PowerMAX offering includes both the conventional techniques and the new technologies. By combining the best industry standard methods with novel technologies unique to Open-Silicon, customers can achieve the lowest power consumption possible for their silicon. The final diagram is show below:
CoreMAX™ was created to build the fastest processor cores in the ASIC world. Processors have a central role in ASIC designs, serving as both a compute engine and a controller for other ASIC blocks. Unlike some logic where clock frequencies are set at discrete values, improving processor performance a few percent often equates to more performance in the final ASIC, and a better overall product. For example, in a mobile media player application, a small improvement in software performance without compromising power consumption may give a significant edge over the competition in terms of device capability or responsiveness.
Also, for some applications overall performance is not as big a factor as cost. For those designs, it may be possible to use CoreMAX to build a processor using a higher-density standard cell library while still achieving strong performance.
Open-Silicon has extensive processor design experience from almost 100 processor implementations, including the techniques in the diagram to right:
In addition to these standard techniques, Open-Silicon offers CoreMAX. The CoreMAX technology comes out of the Open-Silicon acquisition of Zenasis Technologies in 2007 and uses over two million lines of C++ software and several patented techniques to move beyond the limitations of traditional library-based ASIC
design. Built-in CoreMAX functions include design Boolean analysis and optimization, static timing, cell placement, route estimation, and simultaneous optimization at the logical, physical, and transistor levels. Based on the needs of each critical path in the design, CoreMAX may change cells, move cells, or even create new cells on-the-fly, called ZenCells™ performing a library-compatible layout for each new cell and characterizing these cells for use throughout the EDA environment. The new cells offer unique drive strengths and functionality that enable maximum device performance. The combined capabilities are shown in the diagram below:
VariMAX™ addresses increasing process variability. Traditional approaches to variation management involve increased design margins and a large number of extraction and analysis corners. These approaches struggle in technologies like 65nm and 40nm where performance and leakage vary widely across a population of otherwise good devices. Open-Silicon is addressing this with the VariMAX product, which consists of back biasing today and adaptive voltage and frequency control in the future.
Back biasing is a technique that has been used for many years now in the ultra-high volume silicon space, where person-decades could affordably be spent in device optimization. By making this technology available to the ASIC space, Open-Silicon has enabled customers with lower volumes to now enjoy the same leakage and performance variation control and the associated power, performance, and device yield advantages.
Open-Silicon’s back biasing design approach works by controlling the bulk transistor node voltage so that fast, leaky parts are reined in by adaptive calibration of the silicon. The complete diagram is shown below:
The patented TestMAX™ technology addresses test time reduction to lower device cost. Design gate counts continue to grow exponentially, increasing both wafer probe and final test costs. Traditional scan testing frequencies are limited by the power dissipation in the device under test. By profiling the scan vectors for power dissipation, Open-Silicon is able to select those tests with lower thermal impact and power mesh currents and greatly increase their frequency. The net result is a significant reduction in test time, and therefore device cost.
The best part of this technology is that it requires no design changes, is scan-architecture independent, and can be applied on previously taped out designs. TestMAX’s scan shift frequency scaling technology won the SNUG best paper award in 2007.
All designs have a maximum rated power dissipation capability as dictated by the power mesh and the package implemented for the design. Power dissipation beyond this bound causes significant damage to a chip. The effects are, at worst, fatal and, at best, a reduction the device’s useful life. The power planning methodology for designs, in most cases, are implemented with the functional operation of the chip in mind. The power dissipation during test is rarely a factor. Rather, it is the responsibility of the DFT engineer to ensure that the power consumption during test does not exceed the capacity of the power mesh.
The application of ATPG patterns to a DUT (design-under-test) results in switching activity much higher than during functional operation. Since dynamic power is directly proportional to both switching activity and operational frequency, ATPG patterns have to be shifted at a much lower frequency than rated operation frequency to compensate for the increased switching activity. This reduced shift frequency proportionally increases the test time for ATPG patterns since the number of shift cycles form all but a few cycles of a ATPG pattern. This increased test time, in turn, increases test costs and the final cost-per-part.
ATPG patterns are typically generated and applied at a constant shift frequency. Each pattern, regardless of how much power it dissipates, is applied at the same base frequency. However, the dynamic power dissipated on the DUT is pattern-dependent. To put it simply, different patterns have different power dissipation numbers. This difference can be exploited by the DFT engineer to increase the shift frequency of patterns that have low power dissipation numbers until their power dissipation matches power dissipation incurred during functional operation. In this way, the aggregate test time for the pattern set can be safely reduced without damaging the DUT, resulting in the fastest possible scan test and lowest overall cost.