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Highest Performance Interlaken Chip-to-Chip Interface IP

Devendra Godbole, Kalpesh Sanghvi — Open-Silicon
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Supports up to 1.2Tbps and up to 56Gbps SerDes rates

Open-Silicon’s eighth-generation Interlaken IP supports up to 1.2Tbps high-bandwidth performance and up to 56Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high-bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.

The Interlaken protocol is primarily used for high speed chip-to-chip applications. The protocol supports a multiple parallel interface to transmit and receive data from the physical interface or SerDes interface. It also supports packet based interfaces with each packet consisting of multiple bursts, and a simple control work definition to delineate packet and burst boundaries. The protocol is independent of the number of SerDes channels and SerDes rates, and also supports a simple flow control mechanism for back-pressure on any given channel.

The block diagram below shows a functional representation of the multiple aggregate bandwidth interfaces. As an example, a single Interlaken IP instance can be configured in-system to support different Interlaken interfaces: 1×1.2Tbps, 2x600Gbps or 4x300Gbps, leading to a more area efficient and flexible implementation.

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Before we dive into further details, it is very important to address the reasons why Interlaken for chip-to-chip communication is superior to other protocols. Interlaken enables a very narrow interface with the use of SerDes channels. Interlaken supports up to 56G SerDes speed and a maximum bandwidth of 1.2Tbps, and is easily scalable to support higher speeds in the future. Interlaken is a channelized interface, which enables multiple sessions and applications to interact at the same time. Interlaken is highly scalable to support N number of SerDes interfaces and also supports different SerDes rates. The Interlaken protocol allows the interleaving of data transmissions or packet transmission from different channels for low-latency operation.

Here are some of the high-level features of Interlaken IP

  • Supports up to 48 lanes of SerDes, and the SerDes rate supported is up to 56Gbps.
  • Supports a maximum bandwidth of 1.2Tbps with a configuration of 24 lanes of 56G SerDes or a configuration of 48 lanes of 25G SerDes.
  • The user interface is a 128- or 256-bit wide segment, and the total number of user segments supported are 8.
  • Features a pipe-based architecture that is easily scalable to support higher speed and bandwidth.
  • Supports both in-band and out-band flow control on different channels with dual and programmable calendar features.
  • Supports multiple aggregate bandwidth interfaces with multiple cores in a single Interlaken IP, allowing the IP to be configured as 1 core, 2 core or 4 core. For example, in a 1.2Tbps configuration, the IP can work as a single 1.2Tbps IP, or it can work as two 600Gbps IP, or it can work as four 300Gbps IP.
  • Supports retransmit capability, thus reducing the overhead on the application to handle retransmit.
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Interlaken IP Core – Configurability -One Segment User Interface

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Interlaken IP Core – Configurability –Four Segment User Interface

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1.2 Tbps Interlaken IP Core
Support for Forward Error Correction [FEC]

Applications

Now let us understand, at a very high level, where Interlaken fits in and what the different applications are. The diagram below shows the placement of the Interlaken IP and the medium of communication. The Interlaken IP sits between the customer logic, which sends and receives the packets, and the SerDes IP. The chip-to-chip communication medium could be over a printed circuit board, over a backplane or could be over a cable. To the left of the diagram is a list of a few applications that use Interlaken, such as the packet processing engine (also known as a network processing unit), traffic management chip, switching fabric and switch fabric interface that connects to the switching logic, and framers and mappers. Interlaken is also used in memory chips like TCAM and serial memory. Moreover, almost all of the FPGA guys support the Interlaken interface in their FPGA chips. This is just a short list, but there are many other system applications where Interlaken is used.

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  • Packet Processing/NPU
  • Traffic Management
  • Switch Fabric
  • Switch Fabric Interface
  • Framer/Mapper
  • TCAMs
  • Serial Memory (INLK-LA)
  • FPGA etc

Case Study: Data Center System

The left side of the figure below shows a typical data center chassis layout. The line cards and the switch fabric or switch cards are connected to the backplane, and the control/management plane sits at the top. The backplane is a circuit board with sockets that allow line cards and switch cards to be inserted into the socket, connecting them to each other. The line cards provide multiple interfaces to the network. The switch fabric distributes the network traffic across multiple line cards or physical links.

Now let’s look at one piece of the chassis, which is shown in the line card on the right side of the figure. It shows the different chips involved in the line card. Starting from the PHY/optics communicating on the line side; to the framer/mapper to map the SONET/SDH frame to Ethernet and vice-versa; the packet processing/NPU to process the incoming and outgoing Ethernet packets, as well as the TCAM for performing look-ups for the NPU; the traffic management for quality of service; and the fabric I/F to communicate on the system side with the back plane or switch fabric. All of these devices demand very high bandwidth for chip-to-chip communication, and hence, Interlaken is mainly used in such applications.

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When compared to available interconnect protocols, Interlaken offers many advantages in scalability, reduced pin count and data integrity. Its channelization, flow control and burst interleaving features make it appropriate for a wide variety of applications. Finally, the availability of a third party IP core minimizes the cost of adopting the new technology and makes Interlaken the obvious choice for next-generation communications equipment.

Comparison of Interlaken IP Products and Features from Open-Silicon

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As for the roadmap of Interlaken, customers are demanding ever-increasing ASIC bandwidths, from 600G to 800G to 1.2T. Open-Silicon will continue to broaden its envelope to accommodate these requirements and enable future generations of high-bandwidth networking applications. Open-Silicon is a founding member company of The Interlaken Alliance, which was formed to ensure interoperability between different implementations of the Interlaken protocol. Since 2007 Open-Silicon’s Interlaken IP has been deployed in several different tier-1 networking and computing customer products. Many of these products are shipping in production today in the latest technology nodes in multiple foundries. The unique flexibility and configurability built into Open-Silicon’s Interlaken core meets not only today’s technological requirements, but remains fully compatible with older designs.

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