Open-Silicon .:. High Bandwidth Memory (HBM2) Controller and PHY
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Want to get a budgetary quote for 2.5D HBM2 ASIC? Please fill out the Design Requirements Form.

High Bandwidth Memory (HBM2)

High Bandwidth Memory (HBM2) is a high performance 3D-stacked memory solution that leverages the 2.5D technology. The high-performance memory interface uses a wide-interface architecture that allows in achieving very high bandwidth, low power and significantly small form factor. The HBM2 has been adopted by JEDEC as an industry standard.

HBM2 Subsystem IP Solution

Open-Silicon’s subsystem IP solution comprises of the HBM2 Controller, PHY and 2.5D interposer IO thereby addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM2 IP is suitable for applications involving graphics, high-performance computing, high-end networking and communication that require low power and small form factor that are critical to the application.

Solution Differentiators


Open-Silicon’s HBM2 IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM2 protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.

Breaking through the Memory-wall, Open-Silicon’s HBM2 IP subsystem solution is architected and designed to provide the highest performance and flexibility for integrating High Bandwidth Memory directly into next-generation system-in-package (SiP) solutions. The Open-Silicon HBM2 IP fully complies with the HBM2 (>2Gbps per signal) JEDEC® standard.

Key Features

Protocol Controller

–  JEDEC HBM2 DRAM Specification compliant

  • Pseudo-channel mode support
  • Multi stack HBM2 memory support
  • Power down self-refresh modes

–  Low latency Controller Features

  • Per channel data rate – 100Mbps to >2000Mbps/pin
  • Configurable independent channels
  • Memory access optimizations for bandwidth efficiency
  • DFI-like controller/PHY interface
  • Supports 1:1 & 2:1 PHY/controller frequency ratios
  • Memory die diagnostic Features
  • JTAG connectivity for IEEE-1500 access, lane repair, Training and loopback test modes

–  Multiple in-built test & diagnostic features

PHY Layer

  • Ultra-low latency
  • Easily portable across technologies
  • Includes I/O, PLL & DLL
  • Coarse and Fine grain I/O training
  • Low-power HBM memory and PHY modes
  • Complies to ESD requirements
  • Loopback support for testability

Die-to-Die Interposer I/O

  • CMOS I/O with programmable drive strengths
  • 2Gbps/1Ghz DDR with light output loading
  • Up to 5mm interposer trace length support meeting >2Gbps per pin date rate
  • Electrically compatible with JDEC HBM2 spec
  • Optional differential receiver

Want to get a budgetary quote for 2.5D HBM2 ASIC? Please fill out the Design Requirements Form.

For more informatio, visit

JEDEC Standards and Documents are available at


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