High Bandwidth Memory (HBM2) is a high performance 3D-stacked memory solution that leverages the 2.5D technology. The high-performance memory interface uses a wide-interface architecture that allows in achieving very high bandwidth, low power and significantly small form factor. The HBM2 has been adopted by JEDEC as an industry standard.
Open-Silicon’s subsystem IP solution comprises of the HBM2 Controller, PHY and 2.5D interposer IO thereby addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM2 IP is suitable for applications involving graphics, high-performance computing, high-end networking and communication that require low power and small form factor that are critical to the application.
Open-Silicon’s HBM2 IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM2 protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.
Breaking through the Memory-wall, Open-Silicon’s HBM2 IP subsystem solution is architected and designed to provide the highest performance and flexibility for integrating High Bandwidth Memory directly into next-generation system-in-package (SiP) solutions. The Open-Silicon HBM2 IP fully complies with the HBM2 (>2Gbps per signal) JEDEC® standard.
– JEDEC HBM2 DRAM Specification compliant
– Low latency Controller Features
– Multiple in-built test & diagnostic features
Die-to-Die Interposer I/O
Want to get a budgetary quote for 2.5D HBM2 ASIC? Please fill out the Design Requirements Form.
For more informatio, visit www.sifive.com
JEDEC Standards and Documents are available at www.jedec.org/standards-documents
HBM vs. HMC – Comparing Cubes http://eejournal.com
High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D HBM ASIC SiPs https://www.chipestimate.com
Open-Silicon Tapes Out Industry’s First High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in 16nm FF+ http://www.marketwired.com
HBM controller IP holds the key to bandwidth https://www.semiwiki.com
Open-Silicon speaks about its HBM (High Bandwidth Memory) Solution at IP SoC India 2016 in a video interview https://youtu.be
Open-Silicon Announces Comprehensive High Bandwidth Memory (HBM) Gen2 IP Subsystem Solution http://www.marketwired.com