Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

Downloads: HBM ASIC Product Brochure HBM IP-Breaking Through The Memory Wall
HBM IP Subsystem Implementation 2.5D ASIC HBM IP Subsystem Ecosystem
HBM IP Subsystem Solution for High Bandwidth Memory Applications
2.5D SiP Manufacturing Ecosystem for Volume Production of High Bandwidth Memory ASICs
Hardware Enabled Algorithmic Tester For 2.5D HBM Solution

Want to get a budgetary quote for 2.5D HBM ASIC? Please fill out the Design Requirements Form.

High Bandwidth Memory (HBM)

High Bandwidth Memory (HBM) is a high performance 3D-stacked memory solution that leverages the 2.5D technology. The high-performance memory interface uses a wide-interface architecture that allows in achieving very high bandwidth, low power and significantly small form factor. The HBM has been adopted by JEDEC as an industry standard.

HBM Subsystem IP Solution

Open-Silicon’s subsystem IP solution comprises of the HBM Controller, PHY and 2.5D interposer IO thereby addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM IP is suitable for applications involving graphics, high-performance computing, high-end networking and communication that require low power and small form factor that are critical to the application.

Solution Differentiators

HBM-2-5D

Open-Silicon’s HBM IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.

Breaking through the Memory-wall, Open-Silicon’s HBM IP sub-system solution is architected and designed to provide the highest performance and flexibility for integrating High Bandwidth Memory directly into next-generation system-in-package (SiP) solutions. The Open-Silicon HBM IP fully complies with the HBM-Gen2 (2 Gbps per signal) JEDEC® standard.

Key Features

Protocol Controller

–  JEDEC HBM Gen2 DRAM Specification compliant

  • Pseudo-channel mode support
  • Multi Stack HBM Memory Support
  • Power Down self-refresh modes

–  Low latency Controller Features

  • Per channel data rate – 100Mbps to 2000Mbps/pin
  • Configurable Independent channels
  • Memory Access optimizations for Bandwidth efficiency
  • DFI-like Controller/PHY interface
  • Supports 1:1 & 2:1 PHY/controller frequency ratios
  • Memory Die Diagnostic Features
  • JTAG connectivity for IEEE-1500 access, Lane repair, Training and Loopback Test Modes

–  Multiple in-built test & diagnostic features

PHY Layer

  • Ultra-low latency
  • Easily portable across technologies
  • Includes IO, PLL & DLL
  • Coarse and Fine grain IO training
  • Low power HBM memory and PHY modes
  • Complies to ESD Requirements
  • Loopback support for Testability

Die2Die Interposer IO

  • CMOS IO with programmable drive strengths
  • 2Gbps/1Ghz DDR with light output loading
  • Up to 5mm interposer trace length support meeting 2Gbps per pin date rate
  • Electrically compatible with JDEC HBM spec
  • Optional Differential Receiver

 


Downloads: HBM ASIC Product Brochure HBM-Breaking Through The Memory Wall
HBM IP Subsystem Implementation 2.5D ASIC HBM IP Subsystem Ecosystem
HBM IP Subsystem Solution for High Bandwidth Memory Applications
2.5D SiP manufacturing ecosystem for volume production of High Bandwidth Memory ASICs
Hardware Enabled Algorithmic Tester For 2.5D HBM Solution


Want to get a budgetary quote for 2.5D HBM ASIC? Please fill out the Design Requirements Form.


JEDEC Standards and Documents are available at www.jedec.org/standards-documents


References

HBM vs. HMC – Comparing Cubes http://eejournal.com

High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D HBM ASIC SiPs https://www.chipestimate.com

Open-Silicon Tapes Out Industry’s First High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in 16nm FF+  http://www.marketwired.com

HBM controller IP holds the key to bandwidth  https://www.semiwiki.com

Open-Silicon speaks about its HBM (High Bandwidth Memory) Solution at IP SoC India 2016 in a video interview  https://youtu.be

Open-Silicon Announces Comprehensive High Bandwidth Memory (HBM) Gen2 IP Subsystem Solution http://www.marketwired.com

Webinar:  HBM – BREAKING THROUGH “THE MEMORY WALL”