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High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D HBM ASIC SiPs

By Bhupesh Dasila, Dhananjay Wagh — Open-Silicon
Published by chipestimate.com

Explore Open-Silicon IP here.

Open-Silicon’s HBM2 IP Subsystem is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.

Breaking through the Memory-wall, Open-Silicon’s HBM IP sub-system solution is architected and designed to provide the highest performance and flexibility for integrating High Bandwidth Memory directly into next-generation system-in-package (SiP) solutions. The Open-Silicon HBM IP fully complies with the HBM2 (2 Gbps per signal) JEDEC® standard.

Comparison between DDD3 and HBM2

Form Factor

 

Open-Silicon Form Factor

 

Power and Bandwidth

 

Open-Silicon Table 1

 

Open-Silicon’s HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue-isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement while ramping HBM2 ASIC designs into volume production.

 

Open-Silicon and HBM

 

Protocol Controller

  • JEDEC HBM2  DRAM Specification compliant
    • Pseudo-channel mode support
    • Multi Stack HBM Memory Support
    • Power Down self-refresh modes
  • Low latency Controller Features
    • Per channel data rate – 100Mbps to 2000Mbps/pin
    • Configurable Independent channels
    • Memory Access optimizations for Bandwidth efficiency
    • DFI-like Controller/PHY interface
    • Supports 1:1 & 2:1 PHY/controller frequency ratios
    • Memory Die Diagnostic Features
    • JTAG connectivity for IEEE-1500 access, Lane repair, Training and Loopback Test Modes
  • Multiple in-built test & diagnostic features

 

Open-Silicon figure 1 High Performance HBM Controller

 

Figure 1 High Performance HBM Controller

 

Open-Silicon Figure 2 Evidence for Bandwidth

 

Figure 2 Evidence for Bandwidth

PHY Layer

  • Hard-PHY IP
    • Standard-cell P&R based, easily portable across technologies (no circuit-design)
    • Using 3rd party PLL/DLL
    • Leveraging ASIC DDR interface hardening experiences
      (e.g. DDR-DRAM and QDR-SRAM ASIC PHY implementations)
  • First Implementations in TSMC 16FF+
  • Leveraging 2.5D Experience, e.g. on KGD DFT and ESD
  • Proprietary, “DFI-Inspired”, Interface to Controller
    • JEDEC has not specified a PHY – Controller interface for HBM

 

Open-Silicon Figure 3 Physical Hierarchy

 

Figure 3 Physical Hierarchy

HBM I/O Features

  • 1.2V CMOS Output Driver
    • Selectable drive strength for different frequencies and configurations
    • 9,12,15 or 18mA drive strength, linear output current drive
  • 1.2V Powered Receiver
    • CMOS receive mode by default
  • Support for Micro-Bump Pitches of 50um
  • ESD Protection for IO HBM, and CDM protection (150V and 50V respectively)
  • First Implementations in TSMC 16FF+

2.5D Silicon Interposer

 

Open-Silicon HBM Memory and SoC Interface routs on interposer figure 4

 

Figure 4 HBM Memory and SoC Interface routes on interposer

 

Open-Silicon Interposer Spice Simulations Results figure 5

 

Figure 5 Results From Interposer Spice Simulations

Open-Silicon HBM

 

  • Full Subsystem IP Solution
    HBM Controller + PHY + IO IP from one source
  • Performance
    2Gbps per pin data-rate at longer trace lengths with custom I/0
    Bandwidth up-to 256GB/s
  • Proven 2.5D ASIC Design and Packaging
    Three 2.5D ASIC SiP Designs
    HBM interface requires a specialized interposer die-to-die IO
  • Testability
    Probe pads allow reduced total cost of ownership
    Loop back allows for issue-isolation for different IP subsystem components
  • Interoperability
    HBM 2.5D ASIC Design in progress for lead customer
    Lead HBM SoC in TSMC 16nm CoWoSTM will demonstrate:
    IP subsystem <-> HBM die-stack interoperability
  • Ecosystem
    Open-Silicon and the HBM ecosystem is ready to enable supply of HBM2 ASIC SiPs

Conclusion

Open-Silicon’s HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue-isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement while ramping HBM2 ASIC designs into volume production.

Explore Open-Silicon IP here.