Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

“Custom SoCs for IoT: Simplified”
– A Book Focusing on the Emergence of Custom Silicon for IoT Devices.
Download the book:
Custom SoCs for IoT: Simplified

High Bandwidth Memory (HBM2):

Hybrid Memory Cube (HMC): 

HMC ASIC IP Product Brief
HMC FPGA IP Product Brief
HMC Evaluation Board Product Brief

Interlaken IP:

Interlaken White Paper
Interlaken Product Brief
Interlaken- High Speed Chip-to-Chip Interface IP supporting 1.2 Tbps bandwidth and up to 56Gbps SerDes

Networking IP Subsystem:

Interlaken Product Brief-1.2Tbps
PCS IP Product Brief
MCMR FEC IP Product Brief
FlexE IP Product Brief

Partner IP:

Role of 3rd Party IP Selection and Integration in ASICs

2.5D Technology: 

Exploring the 2 5D Interconnect Frontier
2.5D HBM2 ASIC SiP Validation Platform Brochure
HBM IP Subsystem Implementation 2.5D ASIC
2.5D SiP Manufacturing Ecosystem for Volume Production of High Bandwidth Memory ASICs
Hardware Enabled Algorithmic Tester For 2.5D HBM Solution

ARM® Technology Center of Excellence:
Open-Silicon’s ARM Hardening Cortex A Case Studies

ARM® Cortex®-M IoT Edge SoC Platform:
Product Differentiation Using ARM Cortex-M Based IoT Edge SoCs
IoT SoC Platform Demonstration Cortex-M Series
Trust Based IoT Security Mechanism For ARM Based SoCs

SerDes Technology Center of Excellence:
28G SerDes Evaluation Platform
28G SerDes Evaluation Platform Brochure

IoT SoC Platform:
Product Differentiation Using IoT Edge Device SoCs
Industrial IoT System Demonstration
Slash Time-To-Market and Risks: IoT SoC Platforms
Trust Based IoT Security Mechanism for ARM Based SoCs
IoT ASIC Design Using Platforms and IP Ecosystem

IoT Gateway SoC Platform:
Smart City IoT Gateway Reference Platform
Trust Based IoT Security Mechanism for ARM Based SoCs

ASIC and SoC Design:
Greater Debug of a SoC having heterogeneous ARM Cores
UVM based Automated SoC Interconnect Verification Methodology

Prototyping, Software and Validation:
Hardware-Software Co-verification for Successful Custom SoC Projects
Accelerating SOC Verification Using Emulation Platform

Virtual Prototyping:
Virtual Prototyping Brochure
Virtual Prototyping Platform with Flash Memory

Physical Design:
Innovative clock building strategies
Designing with FD-SOI
Advanced Bump Routing Methodology for SoC Designs with Flip Chip
Pipeline based MBIST area overhead optimization using Star Memory System 4.X
ASIC Reliability Verification using Calibre PERC

System Design:
Conquering System Level Issues With LPDDR3 IP Flexibility

Manufacturing:
Challenges in Assembly Implementation of Ultra-Thin Profile Flipchip Package-on-Package