Use the chip browser above to flip through various customer designs and read brief notes about each one.
Design Comments:
- Computing ASIC
- High lane count SerDes
- Unique clocking architecture
Design Comments:
- Dual HyperTransport interfaces
- SerDes
- Flip chip package
Design Comments:
- MIPS Processor
- 65nm
- Open-Silicon CoreMAX Processor Performance Enhancement
- 1.1GHz Clock Speed
Design Comments:
- Open-Silicon VariMAX Technology (adaptive back biasing)
- 65nm
Design Comments:
- Spec handoff
- 90nm
- Many complex IP cores
Design Comments:
- Spec handoff
- 90nm
- Many complex IP cores
Design Comments:
- Networking ASIC
- SerDes
- DDR
Design Comments:
- High lane count SerDes
- Flip chip package
Design Comments:
- Flip chip package
- High gate count
- DDR2
- SerDes
Design Comments:
- PCI Express and XAUI SerDes
- DDR
Design Comments:
- 65nm
- 10Gb SerDes
- Used PowerMAX Power Reduction Technology
Design Comments:
- Flip Chip Package with Dual Row IOs
- High Gate Count: >20M Gates
- DDR3, Analog
Design Comments:
- Networking ASIC
- 90nm
- SerDes, DDR2, HSTL IOs
Design Comments:
- High gate count
- High speed
- CUP IOs
Design Comments:
- Industrial ASIC
- Largest 1T SRAM at TSMC when built
- 19Mb total memory
- High speed
Design Comments:
- Analog ASIC
- Test and package design
- GDS2 Handoff with Open-Silicon manufacturing