Job Openings - India

To apply for any of our open positions, please send an e-mail to careers@open-silicon.com.

Lead IP Applications Engineering
IP Applications Engineering
Test Engineering Manager
ASIC Design Manager/Project Lead
Senior ASIC Design Engineers/ASIC Design Engineers

* Employment Agencies/Recruiters Please Read First

 

Job Title: LEAD IP APPLICATIONS ENGINEERING

Min Educational Qualification: BSEE/MSEE

Relevant Experience: 5+ years experience in ASIC industry with in-depth knowledge and expertise in one or more of the following domains:

  • Front end design and verification of IPs/Bus Protocols
  • Development/Integration of soft IPs like PHY controllers, various embedded processors, memory compilers, etc.
  • Development/Integration of analog design for blocks like PLL, PHY/Serdes, LDO, Bandgap, POR, etc.
  • Development/Integration of foundation IPs like standard cell libraries, IO libraries, Efuse, etc.
  • Experience with front and back-end tools from Magma, Synopsys and Cadence
  • A deep understanding of IP design, ASIC design flow and integration related issues
  • Excellent verbal and written communication skills
  • Experience in the application of third party IP in ASIC design adn the associated issues of selection, qualification, integration and support
  • Experience in customer-facing roles is preferred

Job Description:

  • Part of exciting and challenging IP team for the Silicon Engineering Solutions Group
  • Work very closely with IP vendors and customers in assessing, defining, qualifying, procuring and integrating IPs ranging from standard cells, IOs, memories, PLLs, LDOs, Efuse, to muliti-gigarate Serdes
  • Work very closely with the Open-Silicon sales team to assess and propose the right IP requirements for the ASIC design opportunties
  • Responsible for qualification and integration of various IPs from beginning to the end fo the projects
  • Perform IP analysis from power, performance and area aspects
  • Provide product and technical support to FE, BE, Test and Production Team for various IPs

Job Title: IP APPLICATIONS ENGINEERING

Min Educational Qualification: BSEE/MSEE

Relevant Experience: 2-3 years of experience in IP/library design (standard cells, memories, I/Os, analog blocks, etc.)/applications engineering

  • Experience with frong and back-end (including HSPIC) tools from Magma, Synopsys, and Cadence
  • A deep understanding of IP design, ASIC design flow and integration related issues
  • Excellent verbal and written communication skills
  • Must be able to write scripts for automation and enhancement of IP QA flow

Job Description:

  • Part of exciting and challenging IP team for the Silicon Engineering Solutions Group
  • Qualification and integration of various types of standard cells, memories, I/Os and digital cores in SoCs
  • Perform analog simulations like SSO, etc. on blocks for evalution
  • Provide product and technical support to front-end, back-end, test and production team for various IPs

Job Title: TEST ENGINEERING MANAGER (Job Code: PTM-B-08)

Min Educational Qualification: BSEE/MSEE

Relevant Experience: 7+ years ATE experience

Responsibilities:
Candidate will have responsibility for managing ATE test development group in India. Will create, modify and maintain programs for prototype, productions and characterization of Open-Silicon products. Will be responsible for ensuring a predictable and smooth test flow from design through sort and final test. Will work closely with other functional groups (design, product engineering and QA) to resolve issues and drive product prototype evaluation and production releases. Will also manage outside test resources and drive test partners to achieve high quality deliverables, on time delivery and low cost. Requirements:

 

  • BSEE (MSEE preferred). Or equivalent experience
  • 7+ years ATE hands on experience and managerial skills
  • Familiarity with ATE programming and equipment (Verigy / Teradyne preferred)
  • Good software discipline for creation of ATE programs
  • C and Unix experience
  • Effective communication and analytical skills
  • Design For Test (DFT) experience is a plus

Job Title: ASIC Design Manager/Project Lead (Job Code: ADM-B-06)

Min Educational Qualifications: BSEE /MSEE

Job Description: Relevant Experience with 7 -10 years in ASIC design having led two (or) more designs through physical design Be a part of a dynamic start-up environment and work with a highly motivated, customer - oriented team that focuses on high quality, timely delivery of ASIC Design and Manufacturing services to customers handling multi-million gate ASICs. ASIC Design Manager Should be able to technically lead a team of engineers involved in various phases of ASIC Implementation. Should be able to provide technical support to customers throughout the implementation cycle. Should have successfully led one or more design tape-outs of complex multi-million gate ASICs. Candidates should have exposure to current technology / flow challenges. Good presentation, communication skills and leadership qualities

Requirements: Candidates are expected to have good hands-on experience in the followign areas

  • RTL Synthesis
  • DFT Insertion, test analysis
  • Floor Planning
  • Place & Route
  • Clock Tree Synthesis
  • Static Timing Analysis
  • Cross talk & Power Analysis
  • Physical Verification

    •  

    Candidates should be conversant with industry-standard tools like

     

  • Synopsys
  • Magma
  • Calibre
  • Cadence

    • Job Title: Senior ASIC Design Engineers / ASIC Design Engineers (Job Code: SDE-B-06)

    Min Educational Qualifications: BSEE/MSEE
    Job Description:Relevant Experience 3-6+ years of experience in ASIC design. You will participate in the design tape-outs of complex multi-million gate ASICs with major emphasis on the use of Magma design tools.

    Job Requirements:
    Candidates are expected to have sufficient hands-on experience in the following areas:

    • Place & Route using Magma BlastFusion
    • RTL Synthesis
    • DFT Insertion
    • Test analysis
    • Floor Planning
    • Clock Tree Synthesis
    • Static Timing Analysis
    • Cross talk & Power Analysis
    • Physical Verification

    Candidates should be conversant with industry-standard tools like:

    • Synopsys
    • Magma
    • Calibre
    • Cadence

    Additionally, candidates should have participated in one or more design tape-outs of complex multi-million gate ASICs.

  • ** Employment Agency / Recruiter Policy -- PLEASE READ ** **
    Thank you for your interest in Open-Silicon, Inc. Please note, however, that Open-Silicon does not accept unsolicited resumes from external agencies with which we do not have an existing relationship. Any third-party resume forwarded by agencies/recruiters will be considered property of Open-Silicon and treated as a direct application. This exchange does not constitute an agreement between Open-Silicon and the agency/recruiter. Open-Silicon reserves the right to contact the candidate directly. Employment agencies/recruiters will receive no compensation from Open-Silicon.

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