Job Openings - USA
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Senior ASIC Verification Engineer
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Job Title: SENIOR ASIC VERIFICATION ENGINEER
Educational Requirement: BSEE or equivalent
Relevant Experience: 7+ years experience in ASIC verification, including 4+ years with constrained-random, coverage driven environments
Location: Eau Calire, WI
Description: This position will be part of a small, fast-paced Verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, multi-million gate ASICs. The Senior Verification Engineer is responsible for a wide variety of advanced verification tasks, including designing self-checking testbenches using modern verification techniques; designing verification components such as bus functional models, monitors, and behavioral models; implementing functional coverage and assertions using SystemVerilog; and developing test and functional coverage plans based on device specifications. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing functional coverage results.
Requirements:
- BSEE or equivalent experience
- 7+ years experience in IC verification, including 4+ years with constrained-random, coverage driven verification environments
- Experience working in SystemVerilog and Synopsys VMM
- A solid understanding of object-oriented concepts and experience designing class-based testbenches
- Excellent written and oral communication skills
- Strong debugging skills
- Experience with formal verification tools, hardware design and debug, SystemC and other programming languages are a plus.
- Experience working with OVM, or Specman e is a plus
- Experience working with Emulators, Accelerators and FPGA based prototyping a plus
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