Design Phases

Five Step Design Methodology

Open-Silicon's standardized design methodology addresses the challenges of complex ASIC design in a disciplined manner to produce cost effective ASICs, with on-time schedules that are predictable and give reliable first silicon results.
Following the OpenMODEL™, our methodology is designed to target multiple process technologies at multiple foundries. It opens the design process to the customer allowing valuable customer feedback during the entire process. It follows a disciplined multiphase approach with clear entry and exit criteria, to identify and solve critical design challenges using industry standard tools and libraries that have been proven in several tape-outs across multiple manufacturing processes. The discipline, the checklists, and the distinct phases that are broken down to well-defined steps, help realize reliable first-silicon success.

Our design methodology is composed of 5 distinct phases:

  1. Analyze Phase
  2. Explore Phase
  3. Implement Phase
  4. Converge Phase
  5. Tape Out Phase

Analyze Phase

  • Understand basic architecture requirements.
  • Design planning, design parameter estimation.
  • Identification of critical design challenges.

Inputs:

  • Architecture, design requirements.
  • Data flow diagram and/or paper floor-plan.
  • Sample RTL / Netlist, timing constraints.
  • List of memories and embedded IPs.
  • DFT requirements.
  • Package requirements, I/O plan, power requirements.

Outputs:

  • All design collaterals in place (libraries, memory, I/P, run-sets etc.).
  • Feedback on sample RTL / Netlist.
  • Basic checks on die-size, power, metal layers done.
  • Dry run the sample RTL/Netlist through tool flow for pipe cleaning.
  • Sanity check on chosen package.
  • DFT Physical implementation plan.
  • Critical design challenges identified.
  • Analyze phase checklist completed.

Explore Phase

Objective:

  • Execute complete physical design process.
  • Features, memories, and IP related macros are coded.
  • Basic chip level logic verification is completed.
  • Netlist meets Explore hand-off criteria.

Inputs:

  • Full-chip netlist, Timing constraints.
  • Basic timing, ATPG, physical & power models available for IPs.
  • Top-level data flow diagram, paper floor plan, clock diagram.

Outputs:

  • Floorplan & pad placement completed.
  • Design placed & routed for feasability.
  • Block & chip-level timing analysis completed.
  • Needed constraint refinements identified.
  • Chip level setup timing performance within 10% of design requirements.
  • Dry run the design through IR drop & SI analysis.
  • DFT structures checked by customer.
  • Input netlist verified against implemented netlist.
  • Issues related to input netlist identified & fed back to customer.

Implement Phase

Objective:

  • This is a trial tape-out phase.
  • Complete all physical implementation tasks based on key learnings from Explore phase.
  • Freeze design RTL, floorplan, chip-level ports, memory instances and macros.

Entry Criteria:

  • All architectural features are 100% coded and synthesized.
  • Chip level logic verification run done
  • Netlist meets Implement hand-off criteria.

Inputs:

  • Full-chip netlist, timing constraints.
  • Final timing, ATPG, physical & power models for IPs.
  • Frozen clock architecture diagram
  • Switching activity files.

Outputs:

  • Floorplan, pad placement IO ring frozen.
  • Design placed routed without congestion.
  • Block chip-level timing analysis completed.
  • Chip level setup & hold performance within 5% of design requirements.
  • Chip level power SI requirements within 5 % of design requirements.
  • DFT structures checked by customer; fault coverage meets design requirements.
  • Dry run the design through physical verification flow.
  • Input netlist formally verified against implemented netlist.

Converge Phase

Objective:

  • Chip-level convergence for all performance attributes.
  • Implement any customer ECOs.

Entry Criteria:

  • Entry criteria is the Implement phase closure.

Inputs:

  • Completed Implement phase database.
  • Full-chip ECO netlist (Netlist level ECOs only, no re-synthesis).

Outputs:

  • Completed design layout.
  • Power SI analysis completed with all fixes.
  • Block chip-level setup & hold performance met.
  • Full-chip gate-level simulation completed with timing (Customer).
  • Scan, memBIST JTAG patterns simulation completed with timing.
  • Physical verification run completed violations identified.
  • Input netlist formally verified against implemented netlist.

Tape Out Phase

Objective:

  • Close on the physical database ship.
  • GDSII to fab.

Entry Criteria:

  • Entry criteria is the Converge phase closure, no more ECOs.

Inputs:

  • Physical data from Converge Phase.

Outputs:

  • Clean design layout with all violations fixed.
  • Physical verification flows run clean.
  • Reliability (Power SI) checks run clean.
  • All DFT related check completed.
  • Tape-out paper work completed sent to foundry.
  • Final GDSII data shipped to foundry.