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65nm and Below

A Methodology to Handle Increased Complexity

At 65nm and 45/40nm, lithographic limitations and atomistic doping greatly increase the burden on the design methodology. Variations are up, sensitivities are up, and at the same time the designs themselves are larger and encompass more building blocks than before. From a methodology point of view, focus areas like signal integrity, power integrity, DFM and DFT all take on new complexities as a result. Open-Silicon’s 65nm and 40nm reference flows leverage the best in learning from Open-Silicon’s multiple EDA and foundry partners to put together a solution designed to meet Open-Silicon’s benchmark performance in terms of predictability and reliability.

Key among the issues that need to be managed are a greatly increased process variability, more complex timing behaviors, increased power density and switching currents, and increased layout dependent effects. For example, where power strapping might fix a dynamic IR power hot spot in 90nm, the same approach may be insufficient for newer technologies. Also, variation imposes an increasing burden on device performance and power, and ultimately yield, requiring new approaches to deliver stable volume production.  Open-Silicon's methodology and technology teams would be happy to discuss with you our methodology in detail and help you understand how it could work for you on your design-specific challenges today.