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TestMAX

Lowest Test Costs

 

The patent pending TestMAX™ technology addresses test time reduction to lower device cost. Design gate counts continue to grow exponentially, increasing both wafer probe and final test costs. Traditional scan testing frequencies are limited by the power dissipation in the device under test. By profiling the scan vectors for power dissipation, Open-Silicon is able to select those tests with lower thermal impact and power mesh currents and greatly increase their frequency. The net result is a significant reduction in test time, and therefore device cost.

The best part of this technology is that it requires no design changes, is scan-architecture independent, and can be applied on previously taped out designs. TestMAX’s scan shift frequency scaling technology won the SNUG best paper award in 2007.

How It Works

All designs have a maximum rated power dissipation capability as dictated by the power mesh and the package implemented for the design. Power dissipation beyond this bound causes significant damage to a chip. The effects are, at worst, fatal and, at best, a reduction the device's useful life. The power planning methodology for designs, in most cases, are implemented with the functional operation of the chip in mind. The power dissipation during test is rarely a factor. Rather, it is the responsibility of the DFT engineer to ensure that the power consumption during test does not exceed the capacity of the power mesh.

The application of ATPG patterns to a DUT (design-under-test) results in switching activity much higher than during functional operation. Since dynamic power is directly proportional to both switching activity and operational frequency, ATPG patterns have to be shifted at a much lower frequency than rated operation frequency to compensate for the increased switching activity. This reduced shift frequency proportionally increases the test time for ATPG patterns since the number of shift cycles form all but a few cycles of a ATPG pattern. This increased test time, in turn, increases test costs and the final cost-per-part.

ATPG patterns are typically generated and applied at a constant shift frequency. Each pattern, regardless of how much power it dissipates, is applied at the same base frequency. However, the dynamic power dissipated on the DUT is pattern-dependent. To put it simply, different patterns have different power dissipation numbers. This difference can be exploited by the DFT engineer to increase the shift frequency of patterns that have low power dissipation numbers until their power dissipation matches power dissipation incurred during functional operation. In this way, the aggregate test time for the pattern set can be safely reduced without damaging the DUT, resulting in the fastest possible scan test and lowest overall cost.