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PowerMAX

Designing for the Lowest Power

PowerMAX™ enables design for the lowest possible power. Low power design has moved to the mainstream with 90nm, 65nm, and 40nm, as even designs that were not traditionally power sensitive are now paying close attention to power consumption due to exponential growth in leakage power and higher dynamic power from increasing levels of integration and performance.

A Strong Foundation of Conventional Techniques

In implementing low power designs, Open-Silicon starts with a robust design methodology using conventional techniques. These power savings methods include low-power place-and-route, voltage islands, power gating, clock gating, multi-Vt, and multi-channel length. Some of these techniques have been around for years, while some, such as multi-channel length, are relatively new. Also, some designs will require use of a few techniques, while others may need them all to achieve their market goals.  Open-Silicon's design teams work with our customers to explore the power savings potentials and implementation costs of each, so that the right solution can be put together.

These conventional techniques are shown in the diagram to right:

PowerMAX Technology

PowerMAX adds to this foundation with four new technologies: transistor level transformations, back biasing, power recovery, and custom leakage signoff. This results in the ASIC industry's most complete low power design offering:

PowerMAX's transistor level optimization creates new standard cells on-the-fly to drive down both dynamic and leakage power. In addition to its variability control value, back biasing can also be employed whenever devices enter standby mode to further throttle back leakage power and prolong battery life. Power recovery operates late in the design phase to find timing paths with extra timing margin and replace cells with either higher Vt or lower drive strength equivalents. Finally, with custom leakage signoff Open-Silicon characterizes cell library leakage throughout the temperature range and then uses the actual design junction temperature for the leakage power calculation. Since the leakage power doubles every 15 degrees C, this is required for accurate power estimation.

The complete Open-Silicon PowerMAX offering includes both the conventional techniques and the new technologies.  By combining the best industry standard methods with novel technologies unique to Open-Silicon, customer can achieve the lowest power consumption possible for their silicon.  The final diagram is show below: