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• Silicon Logic Engineering

Silicon Validation

Maximum Yield

The primary goal of Open-Silicon's Product Engineering Group is to maximize the yield of chips from each wafer produced. We monitor yields on regular basis and work closely with both the foundry engineers and the assembly house to address any process drift or changes that may cause yield issues.

As part of the debug process, we perform failure analysis upon any Return Material Request (RMA) and issue 8 Discipline (8D) reports explaining the root cause of the problem and the corrective actions that need to be taken to avoid the problem in the future. We also perform product characterization at different process splits and operating conditions in order to guarantee the quality of the product. Our team assists customers during the validation and debugging phase by providing bench measurement and FIB work if required.

Open-Silicon provides a full suite of die and package qualification including burn-in, ESD, latch up, and Highly Accelerated Stress Test (HAST). We also have the capability of performing second level reliability testing.