• OpenMODEL
• Technology Leadership
• Manufacturing
• Collaboration
  • IP Selection
  • Program Management
  • Design Teams
  • ASICView
• Silicon Logic Engineering

IP Selection

Selection

It is very common for IP to be procured from multiple vendors. Working with each vendor requires careful management of technical, quality, business and legal issues. Taking hard-IP as an example, modern ASICs often integrate multiple high-speed serial interfaces, such as PCIe, USB, and XAUI, memory interfaces such as DDR, CPUs such as ARM, MIPS, and Tensilica, and analog IP, including ADCs, DACs, PLLs, DLLs, and power management blocks, next to library and commodity IP that includes memories, IOs, and standard cells.

Various product development parameters, including time-to-market, cost, features, area, power and performance, drive selection of both technology and IP. For example, a low-voltage device with a unique interface may require a low-power technology, which means the unique interface IP that is needed now has the additional constraint of having to be available in that low-power technology. In addition, the risks associated with a possible lack of proven quality for that IP need to be weighed and taken into account when selecting the IP from various IP vendors.

Finally, as part of the IP selection-process, both compatibility and inter-operability need to be insured. For example, in TSMC’s 90G process multiple voltages can be supported for the IO oxide (1.8, 2.5 and 3.3V). However, not all combinations are supported at this technology node. The selection of IO libraries and PHYs needs to take this into account to ensure compatibility of the selected IP. Another example involves DDR PHYs and their associated controllers where interoperability concerns exist, especially in case when the DDR and the PHY are procured from different vendors, since the standard for the interface between them is new and may to a large extent still be unproven.

Advantages of the OpenMODEL™ for IP Selection

The specific advantages of the IP aggregation model include the following:

• Through economies of scale, the aggregator can cost-effectively develop and employ IP rating procedures and a quality-assurance (QA) platform, minimizing the need for design modification and enhancing chip performance, predictability and reliability.
• Pre-negotiated contracts provide easy and cost-effective access to pre-qualified IP from a wide variety of vendors.
• Strong relationships with IP partners and deep understanding of the IP development and integration process ensure timely IP delivery and integration in the design phase, leading to predictable design and time-to-market schedules.
• Qualification of the IP with the proper process models, EDA tools, and design methodologies for each target silicon process and tool suite maximizes the IP’s reusability for customers.
• Simplified IP integration and the use of high-quality, silicon-proven IP enhances the chance of first-time silicon success.

The selection, procurement and integration of third-party IP is a complex process that has many potential pitfalls along the way. Employing an IP aggregation model with a knowledgeable and experienced organization that works closely with the IP integrator helps overcome IP-related problems and maximizes the IC designer’s chances for first-time silicon success.