Download or Request: Submit ASIC Requirements for Quote 28G SerDes Evaluation Platform Virtual Prototyping Brochure HMC ASIC IP Product Brief

Download or Request: Exploring_the_2 5D_Interconnect_Frontier.pdf

2.5D HBM2 ASIC SiP Validation Platform Brochure

HBM IP Subsystem Implementation 2.5D ASIC

2.5D SiP Manufacturing Ecosystem for Volume Production of High Bandwidth Memory ASICs

Hardware Enabled Algorithmic Tester For 2.5D HBM Solution

Want to get a budgetary quote for 2.5D ASIC? Please fill out the Design Requirements Form.

Open-Silicon™ 2.5D ASIC Capability

Multiple flip-chip die attached to a single, passive silicon interposer with high density microbumps at a 40um pitch Enables connections between dies, as well as connections to the package substrate, using Through-Silicon Vias (TSVs) Finer grain and lower power than MCM solutions – enabling many new applications.

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Proven Open-Silicon™ 2.5D ASIC Methodology

–   Design partitioning – full performance modeling at early stage
–   Physical design and timing closure – joint development of substrate, interposer and logic die
–   DFT – stand-alone wafer level and integrated package test solutions
–   Package design, assembly and reliability


Results From 2.5D ASIC Demo Board:

 2.5D ASIC (Test Chip) Block Diagram
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–  Contains two dual core 1GHz ARM Cortex™-A9 processor die on silicon interposer
–  Connected by AXI D2D interface at (x2) 8GByte/s full-duplex
Fully functional
–  Both CPU die boot and communicate
–  Audio and video demo software running across the die-to-die interface
–  All functional paths operating at targeted speed and power across PVT conditions
–  Test interface running at over 1GHz single-data rate with margin up to 2GHz on next generation
Power – 0.5 pJ/bit for die-to-die interface
Reliability – ESD performance double OSAT requirement


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Click on the image for enlarged view


Download: Exploring_the_2 5D_Interconnect_Frontier.pdf

Want to get a budgetary quote for 2.5D ASIC? Please fill out the Design Requirements Form.

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